@samitouri / QOSamiQemu
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1 /*
2 * Aspeed i2c bus interface for reading from and writing to i2c device registers
3 *
4 * Copyright (c) 2023 IBM Corporation
5 *
6 * Authors:
7 * Stefan Berger <stefanb@linux.ibm.com>
8 *
9 * This work is licensed under the terms of the GNU GPL, version 2 or later.
10 * See the COPYING file in the top-level directory.
11 */
12
13 #include "qemu/osdep.h"
14
15 #include "qtest_aspeed.h"
16 #include "hw/i2c/aspeed_i2c.h"
17
18 static bool aspeed_i2c_is_master_enabled(QTestState *s, uint32_t baseaddr)
19 {
20 return qtest_readl(s, baseaddr + A_I2CC_FUN_CTRL) & A_I2CD_MASTER_EN;
21 }
22
23 static void aspeed_i2c_startup(QTestState *s, uint32_t baseaddr,
24 uint8_t slave_addr, uint8_t reg)
25 {
26 uint32_t v;
27
28 if (!aspeed_i2c_is_master_enabled(s, baseaddr)) {
29 /* one time: enable master */
30 qtest_writel(s, baseaddr + A_I2CC_FUN_CTRL, 0);
31 v = qtest_readl(s, baseaddr + A_I2CC_FUN_CTRL) | A_I2CD_MASTER_EN;
32 qtest_writel(s, baseaddr + A_I2CC_FUN_CTRL, v);
33 }
34
35 /* select device */
36 qtest_writel(s, baseaddr + A_I2CD_BYTE_BUF, slave_addr << 1);
37 qtest_writel(s, baseaddr + A_I2CD_CMD,
38 A_I2CD_M_START_CMD | A_I2CD_M_RX_CMD);
39
40 /* select the register to write to */
41 qtest_writel(s, baseaddr + A_I2CD_BYTE_BUF, reg);
42 qtest_writel(s, baseaddr + A_I2CD_CMD, A_I2CD_M_TX_CMD);
43 }
44
45 static uint32_t aspeed_i2c_read_n(QTestState *s,
46 uint32_t baseaddr, uint8_t slave_addr,
47 uint8_t reg, size_t nbytes)
48 {
49 uint32_t res = 0;
50 uint32_t v;
51 size_t i;
52
53 aspeed_i2c_startup(s, baseaddr, slave_addr, reg);
54
55 for (i = 0; i < nbytes; i++) {
56 qtest_writel(s, baseaddr + A_I2CD_CMD, A_I2CD_M_RX_CMD);
57 v = qtest_readl(s, baseaddr + A_I2CD_BYTE_BUF) >> 8;
58 res |= (v & 0xff) << (i * 8);
59 }
60
61 qtest_writel(s, baseaddr + A_I2CD_CMD, A_I2CD_M_STOP_CMD);
62
63 return res;
64 }
65
66 uint32_t aspeed_i2c_readl(QTestState *s,
67 uint32_t baseaddr, uint8_t slave_addr, uint8_t reg)
68 {
69 return aspeed_i2c_read_n(s, baseaddr, slave_addr, reg, sizeof(uint32_t));
70 }
71
72 uint16_t aspeed_i2c_readw(QTestState *s,
73 uint32_t baseaddr, uint8_t slave_addr, uint8_t reg)
74 {
75 return aspeed_i2c_read_n(s, baseaddr, slave_addr, reg, sizeof(uint16_t));
76 }
77
78 uint8_t aspeed_i2c_readb(QTestState *s,
79 uint32_t baseaddr, uint8_t slave_addr, uint8_t reg)
80 {
81 return aspeed_i2c_read_n(s, baseaddr, slave_addr, reg, sizeof(uint8_t));
82 }
83
84 static void aspeed_i2c_write_n(QTestState *s,
85 uint32_t baseaddr, uint8_t slave_addr,
86 uint8_t reg, uint32_t v, size_t nbytes)
87 {
88 size_t i;
89
90 aspeed_i2c_startup(s, baseaddr, slave_addr, reg);
91
92 for (i = 0; i < nbytes; i++) {
93 qtest_writel(s, baseaddr + A_I2CD_BYTE_BUF, v & 0xff);
94 v >>= 8;
95 qtest_writel(s, baseaddr + A_I2CD_CMD, A_I2CD_M_TX_CMD);
96 }
97
98 qtest_writel(s, baseaddr + A_I2CD_CMD, A_I2CD_M_STOP_CMD);
99 }
100
101 void aspeed_i2c_writel(QTestState *s,
102 uint32_t baseaddr, uint8_t slave_addr,
103 uint8_t reg, uint32_t v)
104 {
105 aspeed_i2c_write_n(s, baseaddr, slave_addr, reg, v, sizeof(v));
106 }
107
108 void aspeed_i2c_writew(QTestState *s,
109 uint32_t baseaddr, uint8_t slave_addr,
110 uint8_t reg, uint16_t v)
111 {
112 aspeed_i2c_write_n(s, baseaddr, slave_addr, reg, v, sizeof(v));
113 }
114
115 void aspeed_i2c_writeb(QTestState *s,
116 uint32_t baseaddr, uint8_t slave_addr,
117 uint8_t reg, uint8_t v)
118 {
119 aspeed_i2c_write_n(s, baseaddr, slave_addr, reg, v, sizeof(v));
120 }