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1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /*
3 *
4 * ASID2 Feature presence and enabled TCR2_EL1 bits test
5 *
6 * Copyright (c) 2025 Linaro Ltd
7 *
8 */
9
10 #include <stdint.h>
11 #include <minilib.h>
12
13 #define ID_AA64MMFR3_EL1 "S3_0_C0_C7_3"
14 #define ID_AA64MMFR4_EL1 "S3_0_C0_C7_4"
15 #define TCR2_EL1 "S3_0_C2_C0_3"
16
17 int main()
18 {
19 /*
20 * Test for presence of ASID2 and three feature bits enabled by it:
21 * https://developer.arm.com/documentation/109697/2025_09/Feature-descriptions/The-Armv9-5-architecture-extension
22 * Bits added are FNG1, FNG0, and A2. These should be RES0 if A2 is
23 * not enabled and read as the written value if A2 is enabled.
24 */
25
26 uint64_t out;
27 uint64_t idreg3;
28 uint64_t idreg4;
29 int tcr2_present;
30 int asid2_present;
31
32 /* Mask is FNG1, FNG0, and A2 */
33 const uint64_t feature_mask = (1ULL << 18 | 1ULL << 17 | 1ULL << 16);
34 const uint64_t in = feature_mask;
35
36 asm("mrs %[idreg3], " ID_AA64MMFR3_EL1 "\n\t"
37 : [idreg3] "=r" (idreg3));
38
39 tcr2_present = ((idreg3 & 0xF) != 0);
40
41 if (!tcr2_present) {
42 ml_printf("TCR2 is not present, cannot perform test");
43 return 0;
44 }
45
46 asm("mrs %[idreg4], " ID_AA64MMFR4_EL1 "\n\t"
47 : [idreg4] "=r" (idreg4));
48
49 asid2_present = ((idreg4 & 0xF00) != 0);
50
51 asm("msr " TCR2_EL1 ", %[x0]\n\t"
52 "mrs %[x1], " TCR2_EL1 "\n\t"
53 : [x1] "=r" (out)
54 : [x0] "r" (in));
55
56 if (asid2_present) {
57 if ((out & feature_mask) == in) {
58 ml_printf("OK\n");
59 return 0;
60 } else {
61 ml_printf("FAIL: ASID2 present, but read value %lx != "
62 "written value %lx\n",
63 out & feature_mask, in);
64 return 1;
65 }
66 } else {
67 if (out == 0) {
68 ml_printf("TCR2_EL1 reads as RES0 as expected\n");
69 return 0;
70 } else {
71 ml_printf("FAIL: ASID2, missing but read value %lx != 0\n",
72 out & feature_mask, in);
73 return 1;
74 }
75 }
76 }