| 1 | #include <stdlib.h> |
| 2 | #include <stdint.h> |
| 3 | #include <assert.h> |
| 4 | |
| 5 | #define MTFSF(FLM, FRB) asm volatile ("mtfsf %0, %1" :: "i" (FLM), "f" (FRB)) |
| 6 | #define MFFS(FRT) asm("mffs %0" : "=f" (FRT)) |
| 7 | #define MFFSCE(FRT) asm("mffsce %0" : "=f" (FRT)) |
| 8 | |
| 9 | #define PPC_BIT_NR(nr) (63 - (nr)) |
| 10 | |
| 11 | #define FP_VE (1ull << PPC_BIT_NR(56)) |
| 12 | #define FP_UE (1ull << PPC_BIT_NR(58)) |
| 13 | #define FP_ZE (1ull << PPC_BIT_NR(59)) |
| 14 | #define FP_XE (1ull << PPC_BIT_NR(60)) |
| 15 | #define FP_NI (1ull << PPC_BIT_NR(61)) |
| 16 | #define FP_RN1 (1ull << PPC_BIT_NR(63)) |
| 17 | |
| 18 | int main(void) |
| 19 | { |
| 20 | uint64_t frt, fpscr; |
| 21 | uint64_t test_value = FP_VE | FP_UE | FP_ZE | |
| 22 | FP_XE | FP_NI | FP_RN1; |
| 23 | MTFSF(0b11111111, test_value); /* set test value to cpu fpscr */ |
| 24 | MFFSCE(frt); |
| 25 | MFFS(fpscr); /* read the value that mffsce stored to cpu fpscr */ |
| 26 | |
| 27 | /* the returned value should be as the cpu fpscr was before */ |
| 28 | assert((frt & 0xff) == test_value); |
| 29 | |
| 30 | /* |
| 31 | * the cpu fpscr last 3 bits should be unchanged |
| 32 | * and enable bits should be unset |
| 33 | */ |
| 34 | assert((fpscr & 0xff) == (test_value & 0x7)); |
| 35 | |
| 36 | return 0; |
| 37 | } |