| 1 | .option norvc |
| 2 | |
| 3 | .text |
| 4 | .global _start |
| 5 | _start: |
| 6 | # Set up vectored interrupts |
| 7 | lla t0, trap |
| 8 | add t0, t0, 1 |
| 9 | csrw mtvec, t0 |
| 10 | |
| 11 | # Enable sw interrupts |
| 12 | csrrsi zero, mie, 0x8 |
| 13 | csrrsi zero, mstatus, 0x8 |
| 14 | |
| 15 | # Engage the double trap: we trigger an machine-level software |
| 16 | # interrupt, which will trap to an illegal instruction |
| 17 | lui t1, 0x02000 |
| 18 | li t0, 1 |
| 19 | sw t0, 0(t1) |
| 20 | |
| 21 | # If we still not went out via the software interrupt route after a |
| 22 | # short while, we failed the test. |
| 23 | lui t0, 0x1 |
| 24 | 0: |
| 25 | addi t0, t0, -1 |
| 26 | bnez t0, 0b |
| 27 | j fail |
| 28 | |
| 29 | trap: |
| 30 | j illegal_insn # Exceptions |
| 31 | j fail # Supervisor software interrupt |
| 32 | j fail |
| 33 | .insn i CUSTOM_0, 0, x0, x0, 0 # Machine software interrupt |
| 34 | j fail |
| 35 | j fail # Supervisor timer interrupt |
| 36 | j fail |
| 37 | j fail # Machine timer interrupt |
| 38 | j fail |
| 39 | j fail # Supervisor external interrupt |
| 40 | j fail |
| 41 | j fail # Machine external interrupt |
| 42 | j fail |
| 43 | j fail # Counter overflow interrupt |
| 44 | j fail |
| 45 | j fail |
| 46 | |
| 47 | illegal_insn: |
| 48 | # Check whether we really got an illegal instruction |
| 49 | csrr t0, mcause |
| 50 | li t1, 2 |
| 51 | bne t0, t1, fail |
| 52 | li a0, 0 |
| 53 | j _exit |
| 54 | fail: |
| 55 | li a0, 1 |
| 56 | _exit: |
| 57 | lla a1, semiargs |
| 58 | li t0, 0x20026 # ADP_Stopped_ApplicationExit |
| 59 | sd t0, 0(a1) |
| 60 | sd a0, 8(a1) |
| 61 | li a0, 0x20 # TARGET_SYS_EXIT_EXTENDED |
| 62 | |
| 63 | # Semihosting call sequence |
| 64 | .balign 16 |
| 65 | slli zero, zero, 0x1f |
| 66 | ebreak |
| 67 | srai zero, zero, 0x7 |
| 68 | j . |
| 69 | |
| 70 | .data |
| 71 | .balign 16 |
| 72 | semiargs: |
| 73 | .space 16 |