| 1 | /* |
| 2 | * Test for MEPC masking bug fix |
| 3 | * |
| 4 | * This test verifies that MEPC properly masks the lower bits according |
| 5 | * to the RISC-V specification when vectored mode bits from STVEC are |
| 6 | * written to MEPC. |
| 7 | */ |
| 8 | |
| 9 | .option norvc |
| 10 | |
| 11 | .text |
| 12 | .global _start |
| 13 | _start: |
| 14 | /* Set up machine trap vector */ |
| 15 | lla t0, machine_trap_handler |
| 16 | csrw mtvec, t0 |
| 17 | |
| 18 | /* Set STVEC with vectored mode (mode bits = 01) */ |
| 19 | li t0, 0x80004001 |
| 20 | csrw stvec, t0 |
| 21 | |
| 22 | /* Clear medeleg to handle exceptions in M-mode */ |
| 23 | csrw medeleg, zero |
| 24 | |
| 25 | /* Trigger illegal instruction exception */ |
| 26 | .word 0xffffffff |
| 27 | |
| 28 | test_completed: |
| 29 | /* Exit with result in a0 */ |
| 30 | /* a0 = 0: success (bits [1:0] were masked) */ |
| 31 | /* a0 != 0: failure (some bits were not masked) */ |
| 32 | j _exit |
| 33 | |
| 34 | machine_trap_handler: |
| 35 | /* Check if illegal instruction (mcause = 2) */ |
| 36 | csrr t0, mcause |
| 37 | li t1, 2 |
| 38 | bne t0, t1, skip_test |
| 39 | |
| 40 | /* Test: Copy STVEC (with mode bits) to MEPC */ |
| 41 | csrr t0, stvec /* t0 = 0x80004001 */ |
| 42 | csrw mepc, t0 /* Write to MEPC */ |
| 43 | csrr t1, mepc /* Read back MEPC */ |
| 44 | |
| 45 | /* Check if bits [1:0] are masked (IALIGN=32 without RVC) */ |
| 46 | andi a0, t1, 3 /* a0 = 0 if both bits masked correctly */ |
| 47 | |
| 48 | /* Set correct return address */ |
| 49 | lla t0, test_completed |
| 50 | csrw mepc, t0 |
| 51 | |
| 52 | skip_test: |
| 53 | mret |
| 54 | |
| 55 | /* Exit with semihosting */ |
| 56 | _exit: |
| 57 | lla a1, semiargs |
| 58 | li t0, 0x20026 /* ADP_Stopped_ApplicationExit */ |
| 59 | sd t0, 0(a1) |
| 60 | sd a0, 8(a1) |
| 61 | li a0, 0x20 /* TARGET_SYS_EXIT_EXTENDED */ |
| 62 | |
| 63 | /* Semihosting call sequence */ |
| 64 | .balign 16 |
| 65 | slli zero, zero, 0x1f |
| 66 | ebreak |
| 67 | srai zero, zero, 0x7 |
| 68 | j . |
| 69 | |
| 70 | .data |
| 71 | .balign 8 |
| 72 | semiargs: |
| 73 | .space 16 |