| 1 | /* |
| 2 | * SPDX-License-Identifier: GPL-2.0-or-later |
| 3 | * Host specific cpu identification for x86. |
| 4 | */ |
| 5 | |
| 6 | #include "qemu/osdep.h" |
| 7 | #include "host/cpuinfo.h" |
| 8 | #ifdef CONFIG_CPUID_H |
| 9 | # include "qemu/cpuid.h" |
| 10 | #endif |
| 11 | |
| 12 | unsigned cpuinfo; |
| 13 | |
| 14 | /* Called both as constructor and (possibly) via other constructors. */ |
| 15 | unsigned __attribute__((constructor)) cpuinfo_init(void) |
| 16 | { |
| 17 | unsigned info = cpuinfo; |
| 18 | |
| 19 | if (info) { |
| 20 | return info; |
| 21 | } |
| 22 | |
| 23 | #ifdef CONFIG_CPUID_H |
| 24 | unsigned max, a, b, c, d, b7 = 0, c7 = 0; |
| 25 | |
| 26 | max = __get_cpuid_max(0, 0); |
| 27 | |
| 28 | if (max >= 7) { |
| 29 | __cpuid_count(7, 0, a, b7, c7, d); |
| 30 | info |= (b7 & bit_BMI ? CPUINFO_BMI1 : 0); |
| 31 | info |= (b7 & bit_BMI2 ? CPUINFO_BMI2 : 0); |
| 32 | } |
| 33 | |
| 34 | if (max >= 1) { |
| 35 | __cpuid(1, a, b, c, d); |
| 36 | |
| 37 | info |= (d & bit_SSE2 ? CPUINFO_SSE2 : 0); |
| 38 | info |= (c & bit_OSXSAVE ? CPUINFO_OSXSAVE : 0); |
| 39 | info |= (c & bit_MOVBE ? CPUINFO_MOVBE : 0); |
| 40 | info |= (c & bit_POPCNT ? CPUINFO_POPCNT : 0); |
| 41 | info |= (c & bit_PCLMUL ? CPUINFO_PCLMUL : 0); |
| 42 | |
| 43 | /* Our AES support requires PSHUFB as well. */ |
| 44 | info |= ((c & bit_AES) && (c & bit_SSSE3) ? CPUINFO_AES : 0); |
| 45 | |
| 46 | /* For AVX features, we must check available and usable. */ |
| 47 | if ((c & bit_AVX) && (c & bit_OSXSAVE)) { |
| 48 | unsigned bv = xgetbv_low(0); |
| 49 | |
| 50 | if ((bv & 6) == 6) { |
| 51 | info |= CPUINFO_AVX1; |
| 52 | info |= (b7 & bit_AVX2 ? CPUINFO_AVX2 : 0); |
| 53 | info |= (c7 & bit_GFNI ? CPUINFO_GFNI : 0); |
| 54 | |
| 55 | if ((bv & 0xe0) == 0xe0) { |
| 56 | info |= (b7 & bit_AVX512F ? CPUINFO_AVX512F : 0); |
| 57 | info |= (b7 & bit_AVX512VL ? CPUINFO_AVX512VL : 0); |
| 58 | info |= (b7 & bit_AVX512BW ? CPUINFO_AVX512BW : 0); |
| 59 | info |= (b7 & bit_AVX512DQ ? CPUINFO_AVX512DQ : 0); |
| 60 | info |= (c7 & bit_AVX512VBMI2 ? CPUINFO_AVX512VBMI2 : 0); |
| 61 | } |
| 62 | |
| 63 | /* |
| 64 | * The Intel SDM has added: |
| 65 | * Processors that enumerate support for Intel® AVX |
| 66 | * (by setting the feature flag CPUID.01H:ECX.AVX[bit 28]) |
| 67 | * guarantee that the 16-byte memory operations performed |
| 68 | * by the following instructions will always be carried |
| 69 | * out atomically: |
| 70 | * - MOVAPD, MOVAPS, and MOVDQA. |
| 71 | * - VMOVAPD, VMOVAPS, and VMOVDQA when encoded with VEX.128. |
| 72 | * - VMOVAPD, VMOVAPS, VMOVDQA32, and VMOVDQA64 when encoded |
| 73 | * with EVEX.128 and k0 (masking disabled). |
| 74 | * Note that these instructions require the linear addresses |
| 75 | * of their memory operands to be 16-byte aligned. |
| 76 | * |
| 77 | * AMD has provided an even stronger guarantee that processors |
| 78 | * with AVX provide 16-byte atomicity for all cacheable, |
| 79 | * naturally aligned single loads and stores, e.g. MOVDQU. |
| 80 | * |
| 81 | * See https://gcc.gnu.org/bugzilla/show_bug.cgi?id=104688 |
| 82 | */ |
| 83 | __cpuid(0, a, b, c, d); |
| 84 | if (c == signature_INTEL_ecx) { |
| 85 | info |= CPUINFO_ATOMIC_VMOVDQA; |
| 86 | } else if (c == signature_AMD_ecx) { |
| 87 | info |= CPUINFO_ATOMIC_VMOVDQA | CPUINFO_ATOMIC_VMOVDQU; |
| 88 | } |
| 89 | } |
| 90 | } |
| 91 | } |
| 92 | |
| 93 | max = __get_cpuid_max(0x8000000, 0); |
| 94 | if (max >= 1) { |
| 95 | __cpuid(0x80000001, a, b, c, d); |
| 96 | info |= (c & bit_LZCNT ? CPUINFO_LZCNT : 0); |
| 97 | } |
| 98 | #endif |
| 99 | |
| 100 | info |= CPUINFO_ALWAYS; |
| 101 | cpuinfo = info; |
| 102 | return info; |
| 103 | } |