target/mips: add Octeon LA* atomic instructions
Implement the Octeon LA* read-modify-write atomic instruction family: LAI/LAID, LAD/LADD, LAA/LAAD, LAS/LASD, LAC/LACD, and LAW/LAWD. These operations are architecturally distinct from SAA/SAAD and are used by existing Octeon user-mode code for atomic counters, bit operations, and exchange-style updates. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: James Hilliard <james.hilliard1@gmail.com> Co-developed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <bd591571-121c-4eac-8ce6-e1e2234dcf3f@linaro.org>
James Hilliard committed
Apr 9, 2026 at 05:54 UTC
006d624b948bf91fd0f491fb44fdef082ff0f3e6
2 files changed
+62
target/mips/tcg/octeon.decode
+17
@@ -68,6 +68,23 @@ V3MULU 011100 ..... ..... ..... 00000 010001 @r3
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SAA 011100 ..... ..... 00000 00000 011000 @saa
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SAAD 011100 ..... ..... 00000 00000 011001 @saa
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+&la base rd
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+&laa base add rd
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+@la ...... base:5 ..... rd:5 ........... &la
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+@laa ...... base:5 add:5 rd:5 ........... &laa
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+LAI 011100 ..... 00000 ..... 00010 011111 @la
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+LAID 011100 ..... 00000 ..... 00011 011111 @la
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+LAD 011100 ..... 00000 ..... 00110 011111 @la
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+LADD 011100 ..... 00000 ..... 00111 011111 @la
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+LAA 011100 ..... ..... ..... 10010 011111 @laa
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+LAAD 011100 ..... ..... ..... 10011 011111 @laa
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+LAS 011100 ..... 00000 ..... 01010 011111 @la
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+LASD 011100 ..... 00000 ..... 01011 011111 @la
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+LAC 011100 ..... 00000 ..... 01110 011111 @la
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+LACD 011100 ..... 00000 ..... 01111 011111 @la
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+LAW 011100 ..... ..... ..... 10110 011111 @laa
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+LAWD 011100 ..... ..... ..... 10111 011111 @laa
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+
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&zcb base
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ZCB 011100 base:5 00000 00000 1110- 011111 &zcb
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target/mips/tcg/octeon_translate.c
+45
@@ -185,6 +185,51 @@ static bool trans_saa(DisasContext *ctx, arg_saa *a, MemOp mop)
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TRANS(SAA, trans_saa, MO_32);
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TRANS(SAAD, trans_saa, MO_64);
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+typedef void AtomicThreeOpFn(TCGv_i64, TCGv_va, TCGv_i64, TCGArg, MemOp);
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+
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+static bool do_atomic_la(DisasContext *ctx, arg_la *a,
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+ AtomicThreeOpFn *atomic_fn, int64_t imm, MemOp mop)
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+{
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+ TCGv_i64 addr = tcg_temp_new_i64();
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+ TCGv_i64 old = tcg_temp_new_i64();
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+ MemOp amo = mo_endian(ctx) | mop | MO_ALIGN;
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+
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+ gen_base_offset_addr(ctx, addr, a->base, 0);
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+
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+ atomic_fn(old, addr, tcg_constant_i64(imm), ctx->mem_idx, amo);
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+ gen_store_gpr(old, a->rd);
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+ return true;
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+}
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+
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+static bool do_atomic_laa(DisasContext *ctx, arg_laa *a,
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+ AtomicThreeOpFn *atomic_fn, MemOp mop)
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+{
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+ TCGv_i64 addr = tcg_temp_new_i64();
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+ TCGv_i64 old = tcg_temp_new_i64();
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+ TCGv_i64 value = tcg_temp_new_i64();
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+ MemOp amo = mo_endian(ctx) | mop | MO_ALIGN;
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+
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+ gen_base_offset_addr(ctx, addr, a->base, 0);
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+ gen_load_gpr(value, a->add);
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+
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+ atomic_fn(old, addr, value, ctx->mem_idx, amo);
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+ gen_store_gpr(old, a->rd);
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+ return true;
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+}
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+
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+TRANS(LAI, do_atomic_la, tcg_gen_atomic_fetch_add_i64, 1, MO_SL);
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+TRANS(LAID, do_atomic_la, tcg_gen_atomic_fetch_add_i64, 1, MO_UQ);
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+TRANS(LAD, do_atomic_la, tcg_gen_atomic_fetch_add_i64, -1, MO_SL);
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+TRANS(LADD, do_atomic_la, tcg_gen_atomic_fetch_add_i64, -1, MO_UQ);
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+TRANS(LAA, do_atomic_laa, tcg_gen_atomic_fetch_add_i64, MO_SL);
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+TRANS(LAAD, do_atomic_laa, tcg_gen_atomic_fetch_add_i64, MO_UQ);
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+TRANS(LAS, do_atomic_la, tcg_gen_atomic_xchg_i64, -1, MO_SL);
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+TRANS(LASD, do_atomic_la, tcg_gen_atomic_xchg_i64, -1, MO_UQ);
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+TRANS(LAC, do_atomic_la, tcg_gen_atomic_xchg_i64, 0, MO_SL);
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+TRANS(LACD, do_atomic_la, tcg_gen_atomic_xchg_i64, 0, MO_UQ);
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+TRANS(LAW, do_atomic_laa, tcg_gen_atomic_xchg_i64, MO_SL);
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+TRANS(LAWD, do_atomic_laa, tcg_gen_atomic_xchg_i64, MO_UQ);
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+
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static bool trans_ZCB(DisasContext *ctx, arg_ZCB *a)
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{
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TCGv_i64 addr = tcg_temp_new_i64();