target/mips: add Octeon VMULU instruction
VMULU multiplies the active Octeon multiplier state by rs, adds rt and queued partial products, returns the low result, and advances P[0]/P[1] with carry limbs. Expand the two-limb accumulator operation inline with TCG so the result and partial-product state stay visible to the optimizer. Add a mips64/mips64el linux-user TCG smoke test for representative Octeon multiplier instruction paths. Include hardware-backed regression coverage for MTP0 P1 zeroing. Signed-off-by: James Hilliard <james.hilliard1@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20260520172313.23777-21-philmd@linaro.org>
James Hilliard committed
May 8, 2026 at 10:55 UTC
0083c9cf2d592a9f9b8e90153cba084e7f229502
3 files changed
+86
target/mips/tcg/octeon.decode
+2
@@ -55,6 +55,8 @@ MTP0 011100 ..... ..... 00000 00000 001001 @r2
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MTP1 011100 ..... ..... 00000 00000 001010 @r2
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MTP2 011100 ..... ..... 00000 00000 001011 @r2
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+VMULU 011100 ..... ..... ..... 00000 001111 @r3
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+
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&saa base rt
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@saa ...... base:5 rt:5 ................ &saa
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SAA 011100 ..... ..... 00000 00000 011000 @saa
target/mips/tcg/octeon_translate.c
+35
@@ -264,3 +264,38 @@ static bool trans_mtp(DisasContext *ctx, arg_r2 *a, unsigned int index)
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TRANS(MTP0, trans_mtp, 0);
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TRANS(MTP1, trans_mtp, 1);
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TRANS(MTP2, trans_mtp, 2);
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+
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+static bool trans_VMULU(DisasContext *ctx, arg_VMULU *a)
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+{
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+ TCGv_i64 x[3], y[3], z[3];
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+ TCGv_i64 tmp = tcg_temp_new_i64();
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+ TCGv_i64 zero = tcg_constant_i64(0);
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+
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+ z[0] = y[0] = tcg_temp_new_i64();
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+ z[1] = y[1] = tcg_temp_new_i64();
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+ z[2] = y[2] = tcg_temp_new_i64();
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+ x[0] = tcg_temp_new_i64();
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+ x[1] = tcg_temp_new_i64();
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+ x[2] = zero;
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+
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+ /* Z = rs * (mpl1 : mpl0) + rt */
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+ gen_load_gpr(tmp, a->rs);
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+ gen_load_gpr(y[0], a->rt);
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+ tcg_gen_mulu2_i64(x[0], x[1], tmp, oct_mpl[0]);
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+ tcg_gen_mulu2_i64(y[1], y[2], tmp, oct_mpl[1]);
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+ tcg_gen_addN_i64(3, z, y, x);
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+
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+ /* X == (0 : p1 : p0) */
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+ x[0] = oct_p[0];
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+ x[1] = oct_p[1];
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+
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+ /* Y == (p1 : p0 : tmp) */
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+ y[0] = tmp;
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+ y[1] = oct_p[0];
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+ y[2] = oct_p[1];
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+
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+ /* (p1 : p0 : rd) = Z + (0 : p1 : p0) */
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+ tcg_gen_addN_i64(3, y, z, x);
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+ gen_store_gpr(tmp, a->rd);
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+ return true;
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+}
tests/tcg/mips/user/isa/octeon/octeon-insns.c
+49
@@ -86,6 +86,53 @@ static uint64_t octeon_sne(uint64_t rs, uint64_t rt)
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return rd;
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}
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+static uint64_t octeon_vmulu(uint64_t mpl0, uint64_t rs, uint64_t rt)
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+{
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+ uint64_t rd;
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+
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+ asm volatile(
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+ "move $8, %[mpl0]\n\t"
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+ "move $9, $0\n\t"
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+ ".word 0x71090008\n\t" /* mtm0 $8, $9 */
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+ "move $8, %[rs]\n\t"
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+ "move $9, %[rt]\n\t"
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+ ".word 0x7109500f\n\t" /* vmulu $10, $8, $9 */
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+ "move %[rd], $10\n\t"
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+ : [rd] "=r" (rd)
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+ : [mpl0] "r" (mpl0), [rs] "r" (rs), [rt] "r" (rt)
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+ : "$8", "$9", "$10");
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+
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+ return rd;
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+}
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+
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+static uint64_t octeon_mtp0_zeroes_p1(void)
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+{
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+ uint64_t rd;
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+
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+ asm volatile(
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+ "move $8, %[mpl0]\n\t"
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+ "move $9, $0\n\t"
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+ ".word 0x71090008\n\t" /* mtm0 $8, $9 */
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+ "move $8, %[p1]\n\t"
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+ "move $9, $0\n\t"
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+ ".word 0x7109000a\n\t" /* mtp1 $8, $9 */
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+ "move $8, $0\n\t"
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+ "move $9, $0\n\t"
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+ ".word 0x71090009\n\t" /* mtp0 $8, $9 */
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+ "move $8, $0\n\t"
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+ "move $9, $0\n\t"
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+ ".word 0x7109500f\n\t" /* vmulu $10, $8, $9 */
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+ "move $8, $0\n\t"
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+ "move $9, $0\n\t"
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+ ".word 0x7109500f\n\t" /* vmulu $10, $8, $9 */
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+ "move %[rd], $10\n\t"
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+ : [rd] "=r" (rd)
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+ : [mpl0] "r" (0ULL), [p1] "r" (1ULL)
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+ : "$8", "$9", "$10");
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+
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+ return rd;
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+}
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+
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int main(void)
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{
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assert(octeon_baddu(0x123, 0x0f0) == 0x13);
@@ -95,6 +142,8 @@ int main(void)
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assert(octeon_seq(0xabc, 0xdef) == 0);
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assert(octeon_sne(0xabc, 0xabc) == 0);
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assert(octeon_sne(0xabc, 0xdef) == 1);
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+ assert(octeon_vmulu(5, 7, 11) == 46);
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+ assert(octeon_mtp0_zeroes_p1() == 0);
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return 0;
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}