target/riscv: Make hpmcounterh return the upper 32-bits
The counter value was not being bitshifted for a hpmcounterh read resulting in hpmcounterh returning the bottom 32-bits. Fixes: cfc96df65e01 ("target/riscv: Remove upper_half from riscv_pmu_ctr_get_fixed_counters_val") Resolves: https://gitlab.com/qemu-project/qemu/-/work_items/3498 Cc: qemu-stable@nongnu.org Signed-off-by: Portia Stephens <portias@oss.tenstorrent.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20260519043352.3685866-1-stephensportia@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Portia Stephens committed
May 19, 2026 at 14:33 UTC
02284108376a6bcfdd56a11de1c6e0bcc3d0e53b
1 file changed
+3
-2
target/riscv/csr.c
+3
-2
@@ -1409,8 +1409,9 @@ RISCVException riscv_pmu_read_ctr(CPURISCVState *env, target_ulong *val,
1409
*/
1410
if (riscv_pmu_ctr_monitor_cycles(env, ctr_idx) ||
1411
riscv_pmu_ctr_monitor_instructions(env, ctr_idx)) {
1412
- *val = riscv_pmu_ctr_get_fixed_counters_val(env, ctr_idx) -
1413
- ctr_prev + ctr_val;
1412
+ uint64_t cntr = riscv_pmu_ctr_get_fixed_counters_val(env, ctr_idx) -
1413
+ ctr_prev + ctr_val;
1414
+ *val = extract64(cntr, start, length);
1415
} else {
1416
*val = ctr_val;
1417
}