Hexagon (target/hexagon) Properly handle Hexagon CPU version
Add the following CPU versions that were previously missing v5 v55 v60 v61 v62 v65 Create a CPUHexagonDef struct to represent the definition of a core Currently contains an enum with the known Hexagon CPU versions Add a field to HexagonCPUClass to note the Hexagon definition Co-authored-by: Matheus Tavares Bernardino <matheus.bernardino@oss.qualcomm.com> Co-authored-by: Brian Cain <brian.cain@oss.qualcomm.com> Signed-off-by: Taylor Simpson <ltaylorsimpson@gmail.com> Reviewed-by: Anton Johansson <anjo@rev.ng> Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com>
Taylor Simpson committed
Feb 17, 2026 at 14:22 UTC
031d8f4bc1575ebdbac9382d2deabdc2c12440d5
3 files changed
+57
-18
target/hexagon/cpu-qom.h
+27
@@ -11,11 +11,38 @@
11
12
#include "hw/core/cpu.h"
13
14
+typedef enum {
15
+ HEX_VER_NONE = 0x00,
16
+ HEX_VER_V5 = 0x04,
17
+ HEX_VER_V55 = 0x05,
18
+ HEX_VER_V60 = 0x60,
19
+ HEX_VER_V61 = 0x61,
20
+ HEX_VER_V62 = 0x62,
21
+ HEX_VER_V65 = 0x65,
22
+ HEX_VER_V66 = 0x66,
23
+ HEX_VER_V67 = 0x67,
24
+ HEX_VER_V68 = 0x68,
25
+ HEX_VER_V69 = 0x69,
26
+ HEX_VER_V71 = 0x71,
27
+ HEX_VER_V73 = 0x73,
28
+ HEX_VER_ANY = 0xff,
29
+} HexagonVersion;
30
+
31
+typedef struct {
32
+ HexagonVersion hex_version;
33
+} HexagonCPUDef;
34
+
35
#define TYPE_HEXAGON_CPU "hexagon-cpu"
36
37
#define HEXAGON_CPU_TYPE_SUFFIX "-" TYPE_HEXAGON_CPU
38
#define HEXAGON_CPU_TYPE_NAME(name) (name HEXAGON_CPU_TYPE_SUFFIX)
39
40
+#define TYPE_HEXAGON_CPU_V5 HEXAGON_CPU_TYPE_NAME("v5")
41
+#define TYPE_HEXAGON_CPU_V55 HEXAGON_CPU_TYPE_NAME("v55")
42
+#define TYPE_HEXAGON_CPU_V60 HEXAGON_CPU_TYPE_NAME("v60")
43
+#define TYPE_HEXAGON_CPU_V61 HEXAGON_CPU_TYPE_NAME("v61")
44
+#define TYPE_HEXAGON_CPU_V62 HEXAGON_CPU_TYPE_NAME("v62")
45
+#define TYPE_HEXAGON_CPU_V65 HEXAGON_CPU_TYPE_NAME("v65")
46
#define TYPE_HEXAGON_CPU_V66 HEXAGON_CPU_TYPE_NAME("v66")
47
#define TYPE_HEXAGON_CPU_V67 HEXAGON_CPU_TYPE_NAME("v67")
48
#define TYPE_HEXAGON_CPU_V68 HEXAGON_CPU_TYPE_NAME("v68")
target/hexagon/cpu.c
+28
-18
@@ -27,13 +27,6 @@
27
#include "exec/gdbstub.h"
28
#include "accel/tcg/cpu-ops.h"
29
30
-static void hexagon_v66_cpu_init(Object *obj) { }
31
-static void hexagon_v67_cpu_init(Object *obj) { }
32
-static void hexagon_v68_cpu_init(Object *obj) { }
33
-static void hexagon_v69_cpu_init(Object *obj) { }
34
-static void hexagon_v71_cpu_init(Object *obj) { }
35
-static void hexagon_v73_cpu_init(Object *obj) { }
36
-
30
static ObjectClass *hexagon_cpu_class_by_name(const char *cpu_model)
31
{
32
ObjectClass *oc;
@@ -377,11 +370,21 @@ static void hexagon_cpu_class_init(ObjectClass *c, const void *data)
370
cc->tcg_ops = &hexagon_tcg_ops;
371
}
372
380
-#define DEFINE_CPU(type_name, initfn) \
381
- { \
382
- .name = type_name, \
383
- .parent = TYPE_HEXAGON_CPU, \
384
- .instance_init = initfn \
373
+static void hexagon_cpu_class_base_init(ObjectClass *c, const void *data)
374
+{
375
+ HexagonCPUClass *mcc = HEXAGON_CPU_CLASS(c);
376
+ /* Make sure all CPU models define a HexagonCPUDef */
377
+ g_assert(!object_class_is_abstract(c) && data != NULL);
378
+ mcc->hex_def = data;
379
+}
380
+
381
+#define DEFINE_CPU(type_name, version) \
382
+ { \
383
+ .name = type_name, \
384
+ .parent = TYPE_HEXAGON_CPU, \
385
+ .class_data = &(const HexagonCPUDef) { \
386
+ .hex_version = version, \
387
+ } \
388
}
389
390
static const TypeInfo hexagon_cpu_type_infos[] = {
@@ -394,13 +397,20 @@ static const TypeInfo hexagon_cpu_type_infos[] = {
397
.abstract = true,
398
.class_size = sizeof(HexagonCPUClass),
399
.class_init = hexagon_cpu_class_init,
400
+ .class_base_init = hexagon_cpu_class_base_init,
401
},
398
- DEFINE_CPU(TYPE_HEXAGON_CPU_V66, hexagon_v66_cpu_init),
399
- DEFINE_CPU(TYPE_HEXAGON_CPU_V67, hexagon_v67_cpu_init),
400
- DEFINE_CPU(TYPE_HEXAGON_CPU_V68, hexagon_v68_cpu_init),
401
- DEFINE_CPU(TYPE_HEXAGON_CPU_V69, hexagon_v69_cpu_init),
402
- DEFINE_CPU(TYPE_HEXAGON_CPU_V71, hexagon_v71_cpu_init),
403
- DEFINE_CPU(TYPE_HEXAGON_CPU_V73, hexagon_v73_cpu_init),
402
+ DEFINE_CPU(TYPE_HEXAGON_CPU_V5, HEX_VER_V5),
403
+ DEFINE_CPU(TYPE_HEXAGON_CPU_V55, HEX_VER_V55),
404
+ DEFINE_CPU(TYPE_HEXAGON_CPU_V60, HEX_VER_V60),
405
+ DEFINE_CPU(TYPE_HEXAGON_CPU_V61, HEX_VER_V61),
406
+ DEFINE_CPU(TYPE_HEXAGON_CPU_V62, HEX_VER_V62),
407
+ DEFINE_CPU(TYPE_HEXAGON_CPU_V65, HEX_VER_V65),
408
+ DEFINE_CPU(TYPE_HEXAGON_CPU_V66, HEX_VER_V66),
409
+ DEFINE_CPU(TYPE_HEXAGON_CPU_V67, HEX_VER_V67),
410
+ DEFINE_CPU(TYPE_HEXAGON_CPU_V68, HEX_VER_V68),
411
+ DEFINE_CPU(TYPE_HEXAGON_CPU_V69, HEX_VER_V69),
412
+ DEFINE_CPU(TYPE_HEXAGON_CPU_V71, HEX_VER_V71),
413
+ DEFINE_CPU(TYPE_HEXAGON_CPU_V73, HEX_VER_V73),
414
};
415
416
DEFINE_TYPES(hexagon_cpu_type_infos)
target/hexagon/cpu.h
+2
@@ -117,6 +117,8 @@ typedef struct HexagonCPUClass {
117
118
DeviceRealize parent_realize;
119
ResettablePhases parent_phases;
120
+
121
+ const HexagonCPUDef *hex_def;
122
} HexagonCPUClass;
123
124
struct ArchCPU {