@samitouri / QOSamiQemu / commits / 0359e41502

target/mips: Inline translator_ld[uw,l,q]() calls

In preparation of removing the translator_ld[uw,l,q]() methods, inline them for the MIPS target, expanding MO_TE by a runtime check on mo_endian(ctx). Mechanical change using the following Coccinelle 'spatch' script: @@ expression env, db, pc; @@ ( - translator_lduw(env, db, pc) + translator_lduw_end(env, db, pc, mo_endian(ctx)) | - translator_ldl(env, db, pc) + translator_ldl_end(env, db, pc, mo_endian(ctx)) | - translator_ldq(env, db, pc) + translator_ldq_end(env, db, pc, mo_endian(ctx)) ) Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20260417042620.35329-4-philmd@linaro.org>

Philippe Mathieu-Daudé committed Nov 27, 2025 at 17:00 UTC 0359e4150236efd0b0e7dff3cec83b9c213f46b6

4 files changed +16 -9

target/mips/tcg/micromips_translate.c.inc

+1 -1

@@ -1629,7 +1629,7 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx)

1629 uint32_t op, minor, minor2, mips32_op;

1630 uint32_t cond, fmt, cc;

1631

1632 - insn = translator_lduw(env, &ctx->base, ctx->base.pc_next + 2);

1632 + insn = translator_lduw_end(env, &ctx->base, ctx->base.pc_next + 2, mo_endian(ctx));

1633 ctx->opcode = (ctx->opcode << 16) | insn;

1634

1635 rt = (ctx->opcode >> 21) & 0x1f;

target/mips/tcg/mips16e_translate.c.inc

+4 -2

@@ -453,7 +453,8 @@ static void decode_i64_mips16(DisasContext *ctx,

453

454 static int decode_extended_mips16_opc(CPUMIPSState *env, DisasContext *ctx)

455 {

456 - int extend = translator_lduw(env, &ctx->base, ctx->base.pc_next + 2);

456 + int extend = translator_lduw_end(env, &ctx->base, ctx->base.pc_next + 2,

457 + mo_endian(ctx));

458 int op, rx, ry, funct, sa;

459 int16_t imm, offset;

460

@@ -686,7 +687,8 @@ static int decode_ase_mips16e(CPUMIPSState *env, DisasContext *ctx)

687 /* No delay slot, so just process as a normal instruction */

688 break;

689 case M16_OPC_JAL:

689 - offset = translator_lduw(env, &ctx->base, ctx->base.pc_next + 2);

690 + offset = translator_lduw_end(env, &ctx->base, ctx->base.pc_next + 2,

691 + mo_endian(ctx));

692 offset = (((ctx->opcode & 0x1f) << 21)

693 | ((ctx->opcode >> 5) & 0x1f) << 16

694 | offset) << 2;

target/mips/tcg/nanomips_translate.c.inc

+3 -2

@@ -3551,7 +3551,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)

3551 int offset;

3552 int imm;

3553

3554 - insn = translator_lduw(env, &ctx->base, ctx->base.pc_next + 2);

3554 + insn = translator_lduw_end(env, &ctx->base, ctx->base.pc_next + 2, mo_endian(ctx));

3555 ctx->opcode = (ctx->opcode << 16) | insn;

3556

3557 rt = extract32(ctx->opcode, 21, 5);

@@ -3665,7 +3665,8 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)

3665 break;

3666 case NM_P48I:

3667 {

3668 - insn = translator_lduw(env, &ctx->base, ctx->base.pc_next + 4);

3668 + insn = translator_lduw_end(env, &ctx->base, ctx->base.pc_next + 4,

3669 + mo_endian(ctx));

3670 target_long addr_off = extract32(ctx->opcode, 0, 16) | insn << 16;

3671 switch (extract32(ctx->opcode, 16, 5)) {

3672 case NM_LI48:

target/mips/tcg/translate.c

+8 -4

@@ -15149,17 +15149,21 @@ static void mips_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)

15149

15150 is_slot = ctx->hflags & MIPS_HFLAG_BMASK;

15151 if (ctx->insn_flags & ISA_NANOMIPS32) {

15152 - ctx->opcode = translator_lduw(env, &ctx->base, ctx->base.pc_next);

15152 + ctx->opcode = translator_lduw_end(env, &ctx->base, ctx->base.pc_next,

15153 + mo_endian(ctx));

15154 insn_bytes = decode_isa_nanomips(env, ctx);

15155 } else if (!(ctx->hflags & MIPS_HFLAG_M16)) {

15155 - ctx->opcode = translator_ldl(env, &ctx->base, ctx->base.pc_next);

15156 + ctx->opcode = translator_ldl_end(env, &ctx->base, ctx->base.pc_next,

15157 + mo_endian(ctx));

15158 insn_bytes = 4;

15159 decode_opc(env, ctx);

15160 } else if (ctx->insn_flags & ASE_MICROMIPS) {

15159 - ctx->opcode = translator_lduw(env, &ctx->base, ctx->base.pc_next);

15161 + ctx->opcode = translator_lduw_end(env, &ctx->base, ctx->base.pc_next,

15162 + mo_endian(ctx));

15163 insn_bytes = decode_isa_micromips(env, ctx);

15164 } else if (ctx->insn_flags & ASE_MIPS16) {

15162 - ctx->opcode = translator_lduw(env, &ctx->base, ctx->base.pc_next);

15165 + ctx->opcode = translator_lduw_end(env, &ctx->base, ctx->base.pc_next,

15166 + mo_endian(ctx));

15167 insn_bytes = decode_ase_mips16e(env, ctx);

15168 } else {

15169 gen_reserved_instruction(ctx);