target/mips: Pass MemOpIdx argument to Load/Store Multiple helpers
In preparation of using the MemOp content in the next commit, pass it as MemOpIdx. Include the access size. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20260417035734.32334-2-philmd@linaro.org>
Philippe Mathieu-Daudé committed
Apr 16, 2026 at 22:28 UTC
0681f9d9522007cd265bc12eea11eb701921f621
2 files changed
+22
-10
target/mips/tcg/ldst_helper.c
+12
-4
@@ -212,8 +212,10 @@ void helper_sdr(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
212
static const int multiple_regs[] = { 16, 17, 18, 19, 20, 21, 22, 23, 30 };
213
214
void helper_lwm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
215
- uint32_t mem_idx)
215
+ uint32_t memop_idx)
216
{
217
+ MemOpIdx oi = memop_idx;
218
+ unsigned mem_idx = get_mmuidx(oi);
219
target_ulong base_reglist = reglist & 0xf;
220
target_ulong do_r31 = reglist & 0x10;
221
@@ -234,8 +236,10 @@ void helper_lwm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
236
}
237
238
void helper_swm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
237
- uint32_t mem_idx)
239
+ uint32_t memop_idx)
240
{
241
+ MemOpIdx oi = memop_idx;
242
+ unsigned mem_idx = get_mmuidx(oi);
243
target_ulong base_reglist = reglist & 0xf;
244
target_ulong do_r31 = reglist & 0x10;
245
@@ -256,8 +260,10 @@ void helper_swm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
260
261
#if defined(TARGET_MIPS64)
262
void helper_ldm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
259
- uint32_t mem_idx)
263
+ uint32_t memop_idx)
264
{
265
+ MemOpIdx oi = memop_idx;
266
+ unsigned mem_idx = get_mmuidx(oi);
267
target_ulong base_reglist = reglist & 0xf;
268
target_ulong do_r31 = reglist & 0x10;
269
@@ -278,8 +284,10 @@ void helper_ldm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
284
}
285
286
void helper_sdm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
281
- uint32_t mem_idx)
287
+ uint32_t memop_idx)
288
{
289
+ MemOpIdx oi = memop_idx;
290
+ unsigned mem_idx = get_mmuidx(oi);
291
target_ulong base_reglist = reglist & 0xf;
292
target_ulong do_r31 = reglist & 0x10;
293
target/mips/tcg/micromips_translate.c.inc
+10
-6
@@ -693,7 +693,8 @@ static void gen_ldst_multiple(DisasContext *ctx, uint32_t opc, int reglist,
693
int base, int16_t offset)
694
{
695
TCGv t0, t1;
696
- TCGv_i32 t2;
696
+ MemOp mop = MO_UNALN;
697
+ MemOpIdx oi;
698
699
if (ctx->hflags & MIPS_HFLAG_BMASK) {
700
gen_reserved_instruction(ctx);
@@ -705,22 +706,25 @@ static void gen_ldst_multiple(DisasContext *ctx, uint32_t opc, int reglist,
706
gen_base_offset_addr(ctx, t0, base, offset);
707
708
t1 = tcg_constant_tl(reglist);
708
- t2 = tcg_constant_i32(ctx->mem_idx);
709
710
save_cpu_state(ctx, 1);
711
switch (opc) {
712
case LWM32:
713
- gen_helper_lwm(tcg_env, t0, t1, t2);
713
+ oi = make_memop_idx(mop | MO_UL, ctx->mem_idx);
714
+ gen_helper_lwm(tcg_env, t0, t1, tcg_constant_i32(oi));
715
break;
716
case SWM32:
716
- gen_helper_swm(tcg_env, t0, t1, t2);
717
+ oi = make_memop_idx(mop | MO_UL, ctx->mem_idx);
718
+ gen_helper_swm(tcg_env, t0, t1, tcg_constant_i32(oi));
719
break;
720
#ifdef TARGET_MIPS64
721
case LDM:
720
- gen_helper_ldm(tcg_env, t0, t1, t2);
722
+ oi = make_memop_idx(mop | MO_UQ, ctx->mem_idx);
723
+ gen_helper_ldm(tcg_env, t0, t1, tcg_constant_i32(oi));
724
break;
725
case SDM:
723
- gen_helper_sdm(tcg_env, t0, t1, t2);
726
+ oi = make_memop_idx(mop | MO_UQ, ctx->mem_idx);
727
+ gen_helper_sdm(tcg_env, t0, t1, tcg_constant_i32(oi));
728
break;
729
#endif
730
}