pnv/mpipl: Preserve CPU registers after crash
Kernel expects the platform to provide CPU registers after pausing execution of the CPUs. Currently only exporting the registers, used by Linux, for generating the /proc/vmcore Reviewed-by: Hari Bathini <hbathini@linux.ibm.com> Reviewed-by: Sourabh Jain <sourabhjain@linux.ibm.com> Signed-off-by: Aditya Gupta <adityag@linux.ibm.com> Tested-by: Shivang Upadhyay <shivangu@linux.ibm.com> Link: https://lore.kernel.org/qemu-devel/20260424083837.214947-6-adityag@linux.ibm.com Signed-off-by: Harsh Prateek Bora <harshpb@linux.ibm.com>
Aditya Gupta committed
Apr 24, 2026 at 14:08 UTC
0991b30c31cdf16e61412c372ac12c76189c5c7b
2 files changed
+214
hw/ppc/pnv_mpipl.c
+154
@@ -8,6 +8,9 @@
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#include "qemu/log.h"
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#include "qemu/units.h"
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#include "system/address-spaces.h"
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+#include "system/cpus.h"
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+#include "system/hw_accel.h"
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+#include "system/memory.h"
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#include "system/runstate.h"
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#include "hw/ppc/pnv.h"
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#include "hw/ppc/pnv_mpipl.h"
@@ -17,6 +20,8 @@
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(pnv->mpipl_state.skiboot_base + MDST_TABLE_OFF)
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#define MDDT_TABLE_RELOCATED \
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(pnv->mpipl_state.skiboot_base + MDDT_TABLE_OFF)
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+#define PROC_DUMP_RELOCATED \
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+ (pnv->mpipl_state.skiboot_base + PROC_DUMP_AREA_OFF)
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/*
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* Preserve the memory regions as pointed by MDST table
@@ -169,9 +174,158 @@ static bool pnv_mpipl_preserve_mem(PnvMachineState *pnv)
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return true;
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}
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+static void do_store_cpu_regs(CPUState *cpu, MpiplPreservedCPUState *state)
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+{
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+ CPUPPCState *env = cpu_env(cpu);
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+ MpiplRegDataHdr *regs_hdr = &state->hdr;
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+ MpiplRegEntry *reg_entries = state->reg_entries;
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+ MpiplRegEntry *curr_reg_entry;
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+ uint32_t num_saved_regs = 0;
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+
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+ cpu_synchronize_state(cpu);
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+
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+ regs_hdr->pir = cpu_to_be32(env->spr[SPR_PIR]);
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+
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+ /* QEMU CPUs are not in Power Saving Mode */
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+ regs_hdr->core_state = 0xff;
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+
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+ regs_hdr->off_regentries = 0;
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+ regs_hdr->num_regentries = cpu_to_be32(NUM_REGS_PER_CPU);
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+
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+ regs_hdr->alloc_size = cpu_to_be32(sizeof(MpiplRegEntry));
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+ regs_hdr->act_size = cpu_to_be32(sizeof(MpiplRegEntry));
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+
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+#define REG_TYPE_GPR 0x1
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+#define REG_TYPE_SPR 0x2
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+#define REG_TYPE_TIMA 0x3
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+
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+/*
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+ * ID numbers used by f/w while populating certain registers
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+ *
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+ * Copied these defines from the linux kernel
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+ */
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+#define REG_ID_NIP 0x7D0
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+#define REG_ID_MSR 0x7D1
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+#define REG_ID_CCR 0x7D2
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+
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+ curr_reg_entry = reg_entries;
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+
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+#define REG_ENTRY(type, num, val) \
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+ do { \
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+ curr_reg_entry->reg_type = cpu_to_be32(type); \
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+ curr_reg_entry->reg_num = cpu_to_be32(num); \
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+ curr_reg_entry->reg_val = cpu_to_be64(val); \
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+ ++curr_reg_entry; \
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+ ++num_saved_regs; \
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+ } while (0)
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+
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+ /* Save the GPRs */
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+ for (int gpr_id = 0; gpr_id < 32; ++gpr_id) {
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+ REG_ENTRY(REG_TYPE_GPR, gpr_id, env->gpr[gpr_id]);
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+ }
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+
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+ REG_ENTRY(REG_TYPE_SPR, SPR_ACOP, env->spr[SPR_ACOP]);
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+ REG_ENTRY(REG_TYPE_SPR, SPR_AMR, env->spr[SPR_AMR]);
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+ REG_ENTRY(REG_TYPE_SPR, SPR_BESCR, env->spr[SPR_BESCR]);
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+ REG_ENTRY(REG_TYPE_SPR, SPR_CFAR, env->spr[SPR_CFAR]);
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+ REG_ENTRY(REG_TYPE_SPR, SPR_CIABR, env->spr[SPR_CIABR]);
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+
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+ REG_ENTRY(REG_TYPE_SPR, SPR_CTR, env->spr[SPR_CTR]);
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+ REG_ENTRY(REG_TYPE_SPR, SPR_CTRL, env->spr[SPR_CTRL]);
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+ REG_ENTRY(REG_TYPE_SPR, SPR_DABR, env->spr[SPR_DABR]);
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+ REG_ENTRY(REG_TYPE_SPR, SPR_DABRX, env->spr[SPR_DABRX]);
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+ REG_ENTRY(REG_TYPE_SPR, SPR_DAR, env->spr[SPR_DAR]);
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+ REG_ENTRY(REG_TYPE_SPR, SPR_DAWR0, env->spr[SPR_DAWR0]);
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+ REG_ENTRY(REG_TYPE_SPR, SPR_DAWR1, env->spr[SPR_DAWR1]);
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+ REG_ENTRY(REG_TYPE_SPR, SPR_DAWRX0, env->spr[SPR_DAWRX0]);
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+ REG_ENTRY(REG_TYPE_SPR, SPR_DAWRX1, env->spr[SPR_DAWRX1]);
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+ REG_ENTRY(REG_TYPE_SPR, SPR_DPDES, env->spr[SPR_DPDES]);
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+ REG_ENTRY(REG_TYPE_SPR, SPR_DSCR, env->spr[SPR_DSCR]);
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+ REG_ENTRY(REG_TYPE_SPR, SPR_DSISR, env->spr[SPR_DSISR]);
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+ REG_ENTRY(REG_TYPE_SPR, SPR_EBBHR, env->spr[SPR_EBBHR]);
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+ REG_ENTRY(REG_TYPE_SPR, SPR_EBBRR, env->spr[SPR_EBBRR]);
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+
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+ REG_ENTRY(REG_TYPE_SPR, SPR_FSCR, env->spr[SPR_FSCR]);
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+
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+ REG_ENTRY(REG_TYPE_SPR, SPR_CTR, env->ctr);
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+ REG_ENTRY(REG_TYPE_SPR, SPR_DAR, env->spr[SPR_DAR]);
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+ REG_ENTRY(REG_TYPE_SPR, SPR_DSISR, env->spr[SPR_DSISR]);
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+ REG_ENTRY(REG_TYPE_SPR, SPR_LR, env->lr);
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+ REG_ENTRY(REG_TYPE_SPR, REG_ID_MSR, env->msr);
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+ REG_ENTRY(REG_TYPE_SPR, REG_ID_NIP, env->nip);
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+ REG_ENTRY(REG_TYPE_SPR, SPR_XER, env->xer);
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+ REG_ENTRY(REG_TYPE_SPR, SPR_SRR0, env->spr[SPR_SRR0]);
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+ REG_ENTRY(REG_TYPE_SPR, SPR_SRR1, env->spr[SPR_SRR1]);
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+ REG_ENTRY(REG_TYPE_SPR, SPR_HSRR0, env->spr[SPR_HSRR0]);
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+ REG_ENTRY(REG_TYPE_SPR, SPR_HSRR1, env->spr[SPR_HSRR1]);
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+ REG_ENTRY(REG_TYPE_SPR, SPR_CFAR, env->spr[SPR_CFAR]);
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+ REG_ENTRY(REG_TYPE_SPR, SPR_HMER, env->spr[SPR_HMER]);
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+ REG_ENTRY(REG_TYPE_SPR, SPR_HMEER, env->spr[SPR_HMEER]);
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+
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+ /*
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+ * Ensure the number of registers saved match the number of
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+ * registers per cpu
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+ *
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+ * This will help catch an error if in future a new register entry
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+ * is added/removed while not modifying NUM_PER_CPU_REGS
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+ */
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+ assert(num_saved_regs == NUM_REGS_PER_CPU);
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+}
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+
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+static bool pnv_mpipl_preserve_cpu_state(PnvMachineState *pnv)
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+{
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+ MachineState *machine = MACHINE(pnv);
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+ uint32_t num_cpus = machine->smp.cpus;
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+ MpiplPreservedCPUState *state;
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+ CPUState *cpu;
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+ AddressSpace *default_as = &address_space_memory;
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+ MemTxResult io_result;
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+ MemTxAttrs attrs;
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+
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+ /* Mark the memory transactions as privileged memory access */
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+ attrs.user = 0;
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+ attrs.memory = 1;
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+
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+ if (pnv->mpipl_state.cpu_states) {
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+ /*
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+ * CPU States might have been allocated from some past crash, free the
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+ * memory to preven memory leak
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+ */
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+ g_free(pnv->mpipl_state.cpu_states);
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+ pnv->mpipl_state.num_cpu_states = 0;
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+ }
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+
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+ pnv->mpipl_state.cpu_states = g_malloc_n(num_cpus,
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+ sizeof(MpiplPreservedCPUState));
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+ pnv->mpipl_state.num_cpu_states = num_cpus;
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+
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+ state = pnv->mpipl_state.cpu_states;
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+
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+ /* Preserve the Processor Dump Area */
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+ io_result = address_space_read(default_as, PROC_DUMP_RELOCATED, attrs,
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+ &pnv->mpipl_state.proc_area, sizeof(MpiplProcDumpArea));
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+ if (io_result != MEMTX_OK) {
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+ qemu_log_mask(LOG_GUEST_ERROR,
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+ "MPIPL: Failed to read Proc Dump Area at: 0x" TARGET_FMT_lx "\n",
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+ PROC_DUMP_RELOCATED);
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+
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+ return false;
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+ }
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+
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+ CPU_FOREACH(cpu) {
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+ do_store_cpu_regs(cpu, state);
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+ ++state;
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+ }
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+
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+ return true;
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+}
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+
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void do_mpipl_preserve(PnvMachineState *pnv)
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{
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+ pause_all_vcpus();
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+
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pnv_mpipl_preserve_mem(pnv);
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+ pnv_mpipl_preserve_cpu_state(pnv);
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/* Mark next boot as Memory-preserving boot */
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pnv->mpipl_state.is_next_boot_mpipl = true;
include/hw/ppc/pnv_mpipl.h
+60
@@ -17,6 +17,10 @@
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typedef struct MdstTableEntry MdstTableEntry;
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typedef struct MdrtTableEntry MdrtTableEntry;
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typedef struct MpiplPreservedState MpiplPreservedState;
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+typedef struct MpiplRegDataHdr MpiplRegDataHdr;
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+typedef struct MpiplRegEntry MpiplRegEntry;
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+typedef struct MpiplProcDumpArea MpiplProcDumpArea;
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+typedef struct MpiplPreservedCPUState MpiplPreservedCPUState;
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/*
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* Following offsets are copied from skiboot source code.
@@ -49,6 +53,8 @@ typedef struct MpiplPreservedState MpiplPreservedState;
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/* HRMOR_BIT copied from skiboot */
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#define HRMOR_BIT (1ull << 63)
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+#define NUM_REGS_PER_CPU 66 /*(32 GPRs, 34 SPRs)*/
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+
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/*
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* Memory Dump Source Table (MDST)
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*
@@ -95,6 +101,55 @@ static_assert(MDST_MAX_ENTRIES == MDDT_MAX_ENTRIES,
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static_assert(MDRT_MAX_ENTRIES >= MDST_MAX_ENTRIES,
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"MDRT should support atleast having number of entries as in MDST");
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+/*
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+ * Processor Dump Area
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+ *
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+ * This contains the information needed for having processor
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+ * state captured during a platform dump.
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+ *
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+ * As mentioned in HDAT, following the P9 specific format
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+ */
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+struct MpiplProcDumpArea {
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+ uint32_t thread_size; /* Size of each thread register entry */
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+#define PROC_DUMP_AREA_VERSION_P9 0x1 /* P9 format */
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+ uint8_t version;
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+ uint8_t reserved[11];
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+ uint64_t alloc_addr; /* Destination memory to place register data */
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+ uint32_t reserved2;
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+ uint32_t alloc_size; /* Allocated size */
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+ uint64_t dest_addr; /* Destination address */
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+ uint32_t reserved3;
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+ uint32_t act_size; /* Actual data size */
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+} QEMU_PACKED;
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+
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+/*
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+ * "Architected Register Data" in the HDAT spec
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+ *
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+ * Acts as a header to the register entries for a particular thread
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+ */
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+struct MpiplRegDataHdr {
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+ uint32_t pir; /* PIR of thread */
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+ uint8_t core_state; /* Stop state of the overall core */
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+ uint8_t reserved[3];
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+ uint32_t off_regentries; /* Offset to Register Entries Array */
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+ uint32_t num_regentries; /* Number of Register Entries in Array */
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+ uint32_t alloc_size; /* Allocated size for each Register Entry */
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+ uint32_t act_size; /* Actual size for each Register Entry */
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+} QEMU_PACKED;
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+
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+struct MpiplRegEntry {
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+ uint32_t reg_type;
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+ uint32_t reg_num;
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+ uint64_t reg_val;
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+} QEMU_PACKED;
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+
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+struct MpiplPreservedCPUState {
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+ MpiplRegDataHdr hdr;
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+
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+ /* Length of 'reg_entries' is hdr.num_regentries */
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+ MpiplRegEntry reg_entries[NUM_REGS_PER_CPU];
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+};
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+
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/* Preserved state to be saved in PnvMachineState */
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struct MpiplPreservedState {
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/* skiboot_base will be valid only after OPAL sends relocated base to SBE */
@@ -103,6 +158,11 @@ struct MpiplPreservedState {
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MdrtTableEntry *mdrt_table;
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uint32_t num_mdrt_entries;
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+
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+ MpiplProcDumpArea proc_area;
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+
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+ MpiplPreservedCPUState *cpu_states;
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+ uint32_t num_cpu_states;
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};
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#endif