hw/riscv/riscv-iommu: Add IPSR.PMIP RW1C support
Add proper RW1C (Read/Write 1 to Clear) support for the IPSR.PMIP (Performance Monitor Interrupt Pending) bit, which was missing from the IPSR register implementation. Signed-off-by: Jay Chang <jay.chang@sifive.com> Reviewed-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Nutty Liu <nutty.liu@hotmail.com> Reviewed-by: Chao Liu <chao.liu.zevorn@gmail.com> Message-ID: <20260325050011.66722-3-jay.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Jay Chang committed
Mar 25, 2026 at 13:00 UTC
0f035e98301aa956d2c64b988a3c1376b28a77d0
2 files changed
+5
hw/riscv/riscv-iommu-bits.h
+1
@@ -189,6 +189,7 @@ enum riscv_iommu_ddtp_modes {
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#define RISCV_IOMMU_REG_IPSR 0x0054
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#define RISCV_IOMMU_IPSR_CIP BIT(0)
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#define RISCV_IOMMU_IPSR_FIP BIT(1)
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+#define RISCV_IOMMU_IPSR_PMIP BIT(2)
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#define RISCV_IOMMU_IPSR_PIP BIT(3)
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enum {
hw/riscv/riscv-iommu.c
+4
@@ -2150,6 +2150,10 @@ static void riscv_iommu_update_ipsr(RISCVIOMMUState *s, uint64_t data)
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ipsr_clr |= RISCV_IOMMU_IPSR_FIP;
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}
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+ if (!(data & RISCV_IOMMU_IPSR_PMIP)) {
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+ ipsr_clr |= RISCV_IOMMU_IPSR_PMIP;
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+ }
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+
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if (data & RISCV_IOMMU_IPSR_PIP) {
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pqcsr = riscv_iommu_reg_get32(s, RISCV_IOMMU_REG_PQCSR);
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