@samitouri / QOSamiQemu / commits / 0ffa9a5b6d

target/mips: Expand TCGv type as 32-bit for XBurst MXU

The MXU extension is only built as 32-bit, so TCGv expands to TCGv_i32. Use the latter which is more explicit. In gen_mxu_s32madd_sub() directly expand: - tcg_gen_ext[u]_tl_i64 -> tcg_gen_ext[u]_i32_i64 - tcg_gen_concat_tl_i64 -> tcg_gen_concat_i32_i64 the rest being mechanical changes. Cc: Siarhei Volkau <lis8215@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Message-Id: <20260401144503.80510-2-philmd@linaro.org>

Philippe Mathieu-Daudé committed Apr 1, 2026 at 16:25 UTC 0ffa9a5b6dc0c3cca98f8d9f3b59c083f1c56c93
1 file changed +977 -977
target/mips/tcg/mxu_translate.c
+977 -977
@@ -606,8 +606,8 @@ enum {
606 #define MXU_OPTN3_PTN7 7
607
608 /* MXU registers */
609 -static TCGv mxu_gpr[NUMBER_OF_MXU_REGISTERS - 1];
610 -static TCGv mxu_CR;
609 +static TCGv_i32 mxu_gpr[NUMBER_OF_MXU_REGISTERS - 1];
610 +static TCGv_i32 mxu_CR;
611
612 static const char mxuregnames[NUMBER_OF_MXU_REGISTERS][4] = {
613 "XR1", "XR2", "XR3", "XR4", "XR5", "XR6", "XR7", "XR8",
@@ -628,42 +628,42 @@ void mxu_translate_init(void)
628 }
629
630 /* MXU General purpose registers moves. */
631 -static inline void gen_load_mxu_gpr(TCGv t, unsigned int reg)
631 +static inline void gen_load_mxu_gpr(TCGv_i32 t, unsigned int reg)
632 {
633 if (reg == 0) {
634 - tcg_gen_movi_tl(t, 0);
634 + tcg_gen_movi_i32(t, 0);
635 } else if (reg <= 15) {
636 - tcg_gen_mov_tl(t, mxu_gpr[reg - 1]);
636 + tcg_gen_mov_i32(t, mxu_gpr[reg - 1]);
637 }
638 }
639
640 -static inline void gen_store_mxu_gpr(TCGv t, unsigned int reg)
640 +static inline void gen_store_mxu_gpr(TCGv_i32 t, unsigned int reg)
641 {
642 if (reg > 0 && reg <= 15) {
643 - tcg_gen_mov_tl(mxu_gpr[reg - 1], t);
643 + tcg_gen_mov_i32(mxu_gpr[reg - 1], t);
644 }
645 }
646
647 -static inline void gen_extract_mxu_gpr(TCGv t, unsigned int reg,
647 +static inline void gen_extract_mxu_gpr(TCGv_i32 t, unsigned int reg,
648 unsigned int ofs, unsigned int len)
649 {
650 if (reg == 0) {
651 - tcg_gen_movi_tl(t, 0);
651 + tcg_gen_movi_i32(t, 0);
652 } else if (reg <= 15) {
653 - tcg_gen_extract_tl(t, mxu_gpr[reg - 1], ofs, len);
653 + tcg_gen_extract_i32(t, mxu_gpr[reg - 1], ofs, len);
654 }
655 }
656
657 /* MXU control register moves. */
658 -static inline void gen_load_mxu_cr(TCGv t)
658 +static inline void gen_load_mxu_cr(TCGv_i32 t)
659 {
660 - tcg_gen_mov_tl(t, mxu_CR);
660 + tcg_gen_mov_i32(t, mxu_CR);
661 }
662
663 -static inline void gen_store_mxu_cr(TCGv t)
663 +static inline void gen_store_mxu_cr(TCGv_i32 t)
664 {
665 /* TODO: Add handling of RW rules for MXU_CR. */
666 - tcg_gen_mov_tl(mxu_CR, t);
666 + tcg_gen_mov_i32(mxu_CR, t);
667 }
668
669 /*
@@ -671,10 +671,10 @@ static inline void gen_store_mxu_cr(TCGv t)
671 */
672 static void gen_mxu_s32i2m(DisasContext *ctx)
673 {
674 - TCGv t0;
674 + TCGv_i32 t0;
675 uint32_t XRa, Rb;
676
677 - t0 = tcg_temp_new();
677 + t0 = tcg_temp_new_i32();
678
679 XRa = extract32(ctx->opcode, 6, 5);
680 Rb = extract32(ctx->opcode, 16, 5);
@@ -692,10 +692,10 @@ static void gen_mxu_s32i2m(DisasContext *ctx)
692 */
693 static void gen_mxu_s32m2i(DisasContext *ctx)
694 {
695 - TCGv t0;
695 + TCGv_i32 t0;
696 uint32_t XRa, Rb;
697
698 - t0 = tcg_temp_new();
698 + t0 = tcg_temp_new_i32();
699
700 XRa = extract32(ctx->opcode, 6, 5);
701 Rb = extract32(ctx->opcode, 16, 5);
@@ -717,11 +717,11 @@ static void gen_mxu_s32m2i(DisasContext *ctx)
717 */
718 static void gen_mxu_s8ldd(DisasContext *ctx, bool postmodify)
719 {
720 - TCGv t0, t1;
720 + TCGv_i32 t0, t1;
721 uint32_t XRa, Rb, s8, optn3;
722
723 - t0 = tcg_temp_new();
724 - t1 = tcg_temp_new();
723 + t0 = tcg_temp_new_i32();
724 + t1 = tcg_temp_new_i32();
725
726 XRa = extract32(ctx->opcode, 6, 4);
727 s8 = extract32(ctx->opcode, 10, 8);
@@ -729,7 +729,7 @@ static void gen_mxu_s8ldd(DisasContext *ctx, bool postmodify)
729 Rb = extract32(ctx->opcode, 21, 5);
730
731 gen_load_gpr(t0, Rb);
732 - tcg_gen_addi_tl(t0, t0, (int8_t)s8);
732 + tcg_gen_addi_i32(t0, t0, (int8_t)s8);
733 if (postmodify) {
734 gen_store_gpr(t0, Rb);
735 }
@@ -737,52 +737,52 @@ static void gen_mxu_s8ldd(DisasContext *ctx, bool postmodify)
737 switch (optn3) {
738 /* XRa[7:0] = tmp8 */
739 case MXU_OPTN3_PTN0:
740 - tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_UB);
740 + tcg_gen_qemu_ld_i32(t1, t0, ctx->mem_idx, MO_UB);
741 gen_load_mxu_gpr(t0, XRa);
742 - tcg_gen_deposit_tl(t0, t0, t1, 0, 8);
742 + tcg_gen_deposit_i32(t0, t0, t1, 0, 8);
743 break;
744 /* XRa[15:8] = tmp8 */
745 case MXU_OPTN3_PTN1:
746 - tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_UB);
746 + tcg_gen_qemu_ld_i32(t1, t0, ctx->mem_idx, MO_UB);
747 gen_load_mxu_gpr(t0, XRa);
748 - tcg_gen_deposit_tl(t0, t0, t1, 8, 8);
748 + tcg_gen_deposit_i32(t0, t0, t1, 8, 8);
749 break;
750 /* XRa[23:16] = tmp8 */
751 case MXU_OPTN3_PTN2:
752 - tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_UB);
752 + tcg_gen_qemu_ld_i32(t1, t0, ctx->mem_idx, MO_UB);
753 gen_load_mxu_gpr(t0, XRa);
754 - tcg_gen_deposit_tl(t0, t0, t1, 16, 8);
754 + tcg_gen_deposit_i32(t0, t0, t1, 16, 8);
755 break;
756 /* XRa[31:24] = tmp8 */
757 case MXU_OPTN3_PTN3:
758 - tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_UB);
758 + tcg_gen_qemu_ld_i32(t1, t0, ctx->mem_idx, MO_UB);
759 gen_load_mxu_gpr(t0, XRa);
760 - tcg_gen_deposit_tl(t0, t0, t1, 24, 8);
760 + tcg_gen_deposit_i32(t0, t0, t1, 24, 8);
761 break;
762 /* XRa = {8'b0, tmp8, 8'b0, tmp8} */
763 case MXU_OPTN3_PTN4:
764 - tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_UB);
765 - tcg_gen_deposit_tl(t0, t1, t1, 16, 16);
764 + tcg_gen_qemu_ld_i32(t1, t0, ctx->mem_idx, MO_UB);
765 + tcg_gen_deposit_i32(t0, t1, t1, 16, 16);
766 break;
767 /* XRa = {tmp8, 8'b0, tmp8, 8'b0} */
768 case MXU_OPTN3_PTN5:
769 - tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_UB);
770 - tcg_gen_shli_tl(t1, t1, 8);
771 - tcg_gen_deposit_tl(t0, t1, t1, 16, 16);
769 + tcg_gen_qemu_ld_i32(t1, t0, ctx->mem_idx, MO_UB);
770 + tcg_gen_shli_i32(t1, t1, 8);
771 + tcg_gen_deposit_i32(t0, t1, t1, 16, 16);
772 break;
773 /* XRa = {{8{sign of tmp8}}, tmp8, {8{sign of tmp8}}, tmp8} */
774 case MXU_OPTN3_PTN6:
775 - tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_SB);
776 - tcg_gen_mov_tl(t0, t1);
777 - tcg_gen_andi_tl(t0, t0, 0xFF00FFFF);
778 - tcg_gen_shli_tl(t1, t1, 16);
779 - tcg_gen_or_tl(t0, t0, t1);
775 + tcg_gen_qemu_ld_i32(t1, t0, ctx->mem_idx, MO_SB);
776 + tcg_gen_mov_i32(t0, t1);
777 + tcg_gen_andi_i32(t0, t0, 0xFF00FFFF);
778 + tcg_gen_shli_i32(t1, t1, 16);
779 + tcg_gen_or_i32(t0, t0, t1);
780 break;
781 /* XRa = {tmp8, tmp8, tmp8, tmp8} */
782 case MXU_OPTN3_PTN7:
783 - tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_UB);
784 - tcg_gen_deposit_tl(t1, t1, t1, 8, 8);
785 - tcg_gen_deposit_tl(t0, t1, t1, 16, 16);
783 + tcg_gen_qemu_ld_i32(t1, t0, ctx->mem_idx, MO_UB);
784 + tcg_gen_deposit_i32(t1, t1, t1, 8, 8);
785 + tcg_gen_deposit_i32(t0, t1, t1, 16, 16);
786 break;
787 }
788
@@ -797,11 +797,11 @@ static void gen_mxu_s8ldd(DisasContext *ctx, bool postmodify)
797 */
798 static void gen_mxu_s8std(DisasContext *ctx, bool postmodify)
799 {
800 - TCGv t0, t1;
800 + TCGv_i32 t0, t1;
801 uint32_t XRa, Rb, s8, optn3;
802
803 - t0 = tcg_temp_new();
804 - t1 = tcg_temp_new();
803 + t0 = tcg_temp_new_i32();
804 + t1 = tcg_temp_new_i32();
805
806 XRa = extract32(ctx->opcode, 6, 4);
807 s8 = extract32(ctx->opcode, 10, 8);
@@ -814,7 +814,7 @@ static void gen_mxu_s8std(DisasContext *ctx, bool postmodify)
814 }
815
816 gen_load_gpr(t0, Rb);
817 - tcg_gen_addi_tl(t0, t0, (int8_t)s8);
817 + tcg_gen_addi_i32(t0, t0, (int8_t)s8);
818 if (postmodify) {
819 gen_store_gpr(t0, Rb);
820 }
@@ -823,23 +823,23 @@ static void gen_mxu_s8std(DisasContext *ctx, bool postmodify)
823 switch (optn3) {
824 /* XRa[7:0] => tmp8 */
825 case MXU_OPTN3_PTN0:
826 - tcg_gen_extract_tl(t1, t1, 0, 8);
826 + tcg_gen_extract_i32(t1, t1, 0, 8);
827 break;
828 /* XRa[15:8] => tmp8 */
829 case MXU_OPTN3_PTN1:
830 - tcg_gen_extract_tl(t1, t1, 8, 8);
830 + tcg_gen_extract_i32(t1, t1, 8, 8);
831 break;
832 /* XRa[23:16] => tmp8 */
833 case MXU_OPTN3_PTN2:
834 - tcg_gen_extract_tl(t1, t1, 16, 8);
834 + tcg_gen_extract_i32(t1, t1, 16, 8);
835 break;
836 /* XRa[31:24] => tmp8 */
837 case MXU_OPTN3_PTN3:
838 - tcg_gen_extract_tl(t1, t1, 24, 8);
838 + tcg_gen_extract_i32(t1, t1, 24, 8);
839 break;
840 }
841
842 - tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_UB);
842 + tcg_gen_qemu_st_i32(t1, t0, ctx->mem_idx, MO_UB);
843 }
844
845 /*
@@ -850,12 +850,12 @@ static void gen_mxu_s8std(DisasContext *ctx, bool postmodify)
850 */
851 static void gen_mxu_s16ldd(DisasContext *ctx, bool postmodify)
852 {
853 - TCGv t0, t1;
853 + TCGv_i32 t0, t1;
854 uint32_t XRa, Rb, optn2;
855 int32_t s10;
856
857 - t0 = tcg_temp_new();
858 - t1 = tcg_temp_new();
857 + t0 = tcg_temp_new_i32();
858 + t1 = tcg_temp_new_i32();
859
860 XRa = extract32(ctx->opcode, 6, 4);
861 s10 = sextract32(ctx->opcode, 10, 9) * 2;
@@ -863,7 +863,7 @@ static void gen_mxu_s16ldd(DisasContext *ctx, bool postmodify)
863 Rb = extract32(ctx->opcode, 21, 5);
864
865 gen_load_gpr(t0, Rb);
866 - tcg_gen_addi_tl(t0, t0, s10);
866 + tcg_gen_addi_i32(t0, t0, s10);
867 if (postmodify) {
868 gen_store_gpr(t0, Rb);
869 }
@@ -871,25 +871,25 @@ static void gen_mxu_s16ldd(DisasContext *ctx, bool postmodify)
871 switch (optn2) {
872 /* XRa[15:0] = tmp16 */
873 case MXU_OPTN2_PTN0:
874 - tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_UW);
874 + tcg_gen_qemu_ld_i32(t1, t0, ctx->mem_idx, MO_UW);
875 gen_load_mxu_gpr(t0, XRa);
876 - tcg_gen_deposit_tl(t0, t0, t1, 0, 16);
876 + tcg_gen_deposit_i32(t0, t0, t1, 0, 16);
877 break;
878 /* XRa[31:16] = tmp16 */
879 case MXU_OPTN2_PTN1:
880 - tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_UW);
880 + tcg_gen_qemu_ld_i32(t1, t0, ctx->mem_idx, MO_UW);
881 gen_load_mxu_gpr(t0, XRa);
882 - tcg_gen_deposit_tl(t0, t0, t1, 16, 16);
882 + tcg_gen_deposit_i32(t0, t0, t1, 16, 16);
883 break;
884 /* XRa = sign_extend(tmp16) */
885 case MXU_OPTN2_PTN2:
886 - tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_SW);
886 + tcg_gen_qemu_ld_i32(t0, t0, ctx->mem_idx, MO_SW);
887 break;
888 /* XRa = {tmp16, tmp16} */
889 case MXU_OPTN2_PTN3:
890 - tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_UW);
891 - tcg_gen_deposit_tl(t0, t1, t1, 0, 16);
892 - tcg_gen_deposit_tl(t0, t1, t1, 16, 16);
890 + tcg_gen_qemu_ld_i32(t1, t0, ctx->mem_idx, MO_UW);
891 + tcg_gen_deposit_i32(t0, t1, t1, 0, 16);
892 + tcg_gen_deposit_i32(t0, t1, t1, 16, 16);
893 break;
894 }
895
@@ -904,12 +904,12 @@ static void gen_mxu_s16ldd(DisasContext *ctx, bool postmodify)
904 */
905 static void gen_mxu_s16std(DisasContext *ctx, bool postmodify)
906 {
907 - TCGv t0, t1;
907 + TCGv_i32 t0, t1;
908 uint32_t XRa, Rb, optn2;
909 int32_t s10;
910
911 - t0 = tcg_temp_new();
912 - t1 = tcg_temp_new();
911 + t0 = tcg_temp_new_i32();
912 + t1 = tcg_temp_new_i32();
913
914 XRa = extract32(ctx->opcode, 6, 4);
915 s10 = sextract32(ctx->opcode, 10, 9) * 2;
@@ -922,7 +922,7 @@ static void gen_mxu_s16std(DisasContext *ctx, bool postmodify)
922 }
923
924 gen_load_gpr(t0, Rb);
925 - tcg_gen_addi_tl(t0, t0, s10);
925 + tcg_gen_addi_i32(t0, t0, s10);
926 if (postmodify) {
927 gen_store_gpr(t0, Rb);
928 }
@@ -931,15 +931,15 @@ static void gen_mxu_s16std(DisasContext *ctx, bool postmodify)
931 switch (optn2) {
932 /* XRa[15:0] => tmp16 */
933 case MXU_OPTN2_PTN0:
934 - tcg_gen_extract_tl(t1, t1, 0, 16);
934 + tcg_gen_extract_i32(t1, t1, 0, 16);
935 break;
936 /* XRa[31:16] => tmp16 */
937 case MXU_OPTN2_PTN1:
938 - tcg_gen_extract_tl(t1, t1, 16, 16);
938 + tcg_gen_extract_i32(t1, t1, 16, 16);
939 break;
940 }
941
942 - tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_UW);
942 + tcg_gen_qemu_st_i32(t1, t0, ctx->mem_idx, MO_UW);
943 }
944
945 /*
@@ -953,11 +953,11 @@ static void gen_mxu_s16std(DisasContext *ctx, bool postmodify)
953 */
954 static void gen_mxu_s32mul(DisasContext *ctx, bool mulu)
955 {
956 - TCGv t0, t1;
956 + TCGv_i32 t0, t1;
957 uint32_t XRa, XRd, rs, rt;
958
959 - t0 = tcg_temp_new();
960 - t1 = tcg_temp_new();
959 + t0 = tcg_temp_new_i32();
960 + t1 = tcg_temp_new_i32();
961
962 XRa = extract32(ctx->opcode, 6, 4);
963 XRd = extract32(ctx->opcode, 10, 4);
@@ -965,20 +965,20 @@ static void gen_mxu_s32mul(DisasContext *ctx, bool mulu)
965 rt = extract32(ctx->opcode, 21, 5);
966
967 if (unlikely(rs == 0 || rt == 0)) {
968 - tcg_gen_movi_tl(t0, 0);
969 - tcg_gen_movi_tl(t1, 0);
968 + tcg_gen_movi_i32(t0, 0);
969 + tcg_gen_movi_i32(t1, 0);
970 } else {
971 gen_load_gpr(t0, rs);
972 gen_load_gpr(t1, rt);
973
974 if (mulu) {
975 - tcg_gen_mulu2_tl(t0, t1, t0, t1);
975 + tcg_gen_mulu2_i32(t0, t1, t0, t1);
976 } else {
977 - tcg_gen_muls2_tl(t0, t1, t0, t1);
977 + tcg_gen_muls2_i32(t0, t1, t0, t1);
978 }
979 }
980 - tcg_gen_mov_tl(cpu_HI[0], t1);
981 - tcg_gen_mov_tl(cpu_LO[0], t0);
980 + tcg_gen_mov_i32(cpu_HI[0], t1);
981 + tcg_gen_mov_i32(cpu_LO[0], t0);
982 gen_store_mxu_gpr(t1, XRa);
983 gen_store_mxu_gpr(t0, XRd);
984 }
@@ -993,13 +993,13 @@ static void gen_mxu_s32mul(DisasContext *ctx, bool mulu)
993 static void gen_mxu_d16mul(DisasContext *ctx, bool fractional,
994 bool packed_result)
995 {
996 - TCGv t0, t1, t2, t3;
996 + TCGv_i32 t0, t1, t2, t3;
997 uint32_t XRa, XRb, XRc, XRd, optn2;
998
999 - t0 = tcg_temp_new();
1000 - t1 = tcg_temp_new();
1001 - t2 = tcg_temp_new();
1002 - t3 = tcg_temp_new();
999 + t0 = tcg_temp_new_i32();
1000 + t1 = tcg_temp_new_i32();
1001 + t2 = tcg_temp_new_i32();
1002 + t3 = tcg_temp_new_i32();
1003
1004 XRa = extract32(ctx->opcode, 6, 4);
1005 XRb = extract32(ctx->opcode, 10, 4);
@@ -1014,64 +1014,64 @@ static void gen_mxu_d16mul(DisasContext *ctx, bool fractional,
1014 */
1015
1016 gen_load_mxu_gpr(t1, XRb);
1017 - tcg_gen_sextract_tl(t0, t1, 0, 16);
1018 - tcg_gen_sextract_tl(t1, t1, 16, 16);
1017 + tcg_gen_sextract_i32(t0, t1, 0, 16);
1018 + tcg_gen_sextract_i32(t1, t1, 16, 16);
1019 gen_load_mxu_gpr(t3, XRc);
1020 - tcg_gen_sextract_tl(t2, t3, 0, 16);
1021 - tcg_gen_sextract_tl(t3, t3, 16, 16);
1020 + tcg_gen_sextract_i32(t2, t3, 0, 16);
1021 + tcg_gen_sextract_i32(t3, t3, 16, 16);
1022
1023 switch (optn2) {
1024 case MXU_OPTN2_WW: /* XRB.H*XRC.H == lop, XRB.L*XRC.L == rop */
1025 - tcg_gen_mul_tl(t3, t1, t3);
1026 - tcg_gen_mul_tl(t2, t0, t2);
1025 + tcg_gen_mul_i32(t3, t1, t3);
1026 + tcg_gen_mul_i32(t2, t0, t2);
1027 break;
1028 case MXU_OPTN2_LW: /* XRB.L*XRC.H == lop, XRB.L*XRC.L == rop */
1029 - tcg_gen_mul_tl(t3, t0, t3);
1030 - tcg_gen_mul_tl(t2, t0, t2);
1029 + tcg_gen_mul_i32(t3, t0, t3);
1030 + tcg_gen_mul_i32(t2, t0, t2);
1031 break;
1032 case MXU_OPTN2_HW: /* XRB.H*XRC.H == lop, XRB.H*XRC.L == rop */
1033 - tcg_gen_mul_tl(t3, t1, t3);
1034 - tcg_gen_mul_tl(t2, t1, t2);
1033 + tcg_gen_mul_i32(t3, t1, t3);
1034 + tcg_gen_mul_i32(t2, t1, t2);
1035 break;
1036 case MXU_OPTN2_XW: /* XRB.L*XRC.H == lop, XRB.H*XRC.L == rop */
1037 - tcg_gen_mul_tl(t3, t0, t3);
1038 - tcg_gen_mul_tl(t2, t1, t2);
1037 + tcg_gen_mul_i32(t3, t0, t3);
1038 + tcg_gen_mul_i32(t2, t1, t2);
1039 break;
1040 }
1041 if (fractional) {
1042 TCGLabel *l_done = gen_new_label();
1043 - TCGv rounding = tcg_temp_new();
1043 + TCGv_i32 rounding = tcg_temp_new_i32();
1044
1045 - tcg_gen_shli_tl(t3, t3, 1);
1046 - tcg_gen_shli_tl(t2, t2, 1);
1047 - tcg_gen_andi_tl(rounding, mxu_CR, 0x2);
1048 - tcg_gen_brcondi_tl(TCG_COND_EQ, rounding, 0, l_done);
1045 + tcg_gen_shli_i32(t3, t3, 1);
1046 + tcg_gen_shli_i32(t2, t2, 1);
1047 + tcg_gen_andi_i32(rounding, mxu_CR, 0x2);
1048 + tcg_gen_brcondi_i32(TCG_COND_EQ, rounding, 0, l_done);
1049 if (packed_result) {
1050 TCGLabel *l_apply_bias_l = gen_new_label();
1051 TCGLabel *l_apply_bias_r = gen_new_label();
1052 TCGLabel *l_half_done = gen_new_label();
1053 - TCGv bias = tcg_temp_new();
1053 + TCGv_i32 bias = tcg_temp_new_i32();
1054
1055 /*
1056 * D16MULF supports unbiased rounding aka "bankers rounding",
1057 * "round to even", "convergent rounding"
1058 */
1059 - tcg_gen_andi_tl(bias, mxu_CR, 0x4);
1060 - tcg_gen_brcondi_tl(TCG_COND_NE, bias, 0, l_apply_bias_l);
1061 - tcg_gen_andi_tl(t0, t3, 0x1ffff);
1062 - tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0x8000, l_half_done);
1059 + tcg_gen_andi_i32(bias, mxu_CR, 0x4);
1060 + tcg_gen_brcondi_i32(TCG_COND_NE, bias, 0, l_apply_bias_l);
1061 + tcg_gen_andi_i32(t0, t3, 0x1ffff);
1062 + tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0x8000, l_half_done);
1063 gen_set_label(l_apply_bias_l);
1064 - tcg_gen_addi_tl(t3, t3, 0x8000);
1064 + tcg_gen_addi_i32(t3, t3, 0x8000);
1065 gen_set_label(l_half_done);
1066 - tcg_gen_brcondi_tl(TCG_COND_NE, bias, 0, l_apply_bias_r);
1067 - tcg_gen_andi_tl(t0, t2, 0x1ffff);
1068 - tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0x8000, l_done);
1066 + tcg_gen_brcondi_i32(TCG_COND_NE, bias, 0, l_apply_bias_r);
1067 + tcg_gen_andi_i32(t0, t2, 0x1ffff);
1068 + tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0x8000, l_done);
1069 gen_set_label(l_apply_bias_r);
1070 - tcg_gen_addi_tl(t2, t2, 0x8000);
1070 + tcg_gen_addi_i32(t2, t2, 0x8000);
1071 } else {
1072 /* D16MULE doesn't support unbiased rounding */
1073 - tcg_gen_addi_tl(t3, t3, 0x8000);
1074 - tcg_gen_addi_tl(t2, t2, 0x8000);
1073 + tcg_gen_addi_i32(t3, t3, 0x8000);
1074 + tcg_gen_addi_i32(t2, t2, 0x8000);
1075 }
1076 gen_set_label(l_done);
1077 }
@@ -1079,9 +1079,9 @@ static void gen_mxu_d16mul(DisasContext *ctx, bool fractional,
1079 gen_store_mxu_gpr(t3, XRa);
1080 gen_store_mxu_gpr(t2, XRd);
1081 } else {
1082 - tcg_gen_andi_tl(t3, t3, 0xffff0000);
1083 - tcg_gen_shri_tl(t2, t2, 16);
1084 - tcg_gen_or_tl(t3, t3, t2);
1082 + tcg_gen_andi_i32(t3, t3, 0xffff0000);
1083 + tcg_gen_shri_i32(t2, t2, 16);
1084 + tcg_gen_or_i32(t3, t3, t2);
1085 gen_store_mxu_gpr(t3, XRa);
1086 }
1087 }
@@ -1097,13 +1097,13 @@ static void gen_mxu_d16mul(DisasContext *ctx, bool fractional,
1097 static void gen_mxu_d16mac(DisasContext *ctx, bool fractional,
1098 bool packed_result)
1099 {
1100 - TCGv t0, t1, t2, t3;
1100 + TCGv_i32 t0, t1, t2, t3;
1101 uint32_t XRa, XRb, XRc, XRd, optn2, aptn2;
1102
1103 - t0 = tcg_temp_new();
1104 - t1 = tcg_temp_new();
1105 - t2 = tcg_temp_new();
1106 - t3 = tcg_temp_new();
1103 + t0 = tcg_temp_new_i32();
1104 + t1 = tcg_temp_new_i32();
1105 + t2 = tcg_temp_new_i32();
1106 + t3 = tcg_temp_new_i32();
1107
1108 XRa = extract32(ctx->opcode, 6, 4);
1109 XRb = extract32(ctx->opcode, 10, 4);
@@ -1113,90 +1113,90 @@ static void gen_mxu_d16mac(DisasContext *ctx, bool fractional,
1113 aptn2 = extract32(ctx->opcode, 24, 2);
1114
1115 gen_load_mxu_gpr(t1, XRb);
1116 - tcg_gen_sextract_tl(t0, t1, 0, 16);
1117 - tcg_gen_sextract_tl(t1, t1, 16, 16);
1116 + tcg_gen_sextract_i32(t0, t1, 0, 16);
1117 + tcg_gen_sextract_i32(t1, t1, 16, 16);
1118
1119 gen_load_mxu_gpr(t3, XRc);
1120 - tcg_gen_sextract_tl(t2, t3, 0, 16);
1121 - tcg_gen_sextract_tl(t3, t3, 16, 16);
1120 + tcg_gen_sextract_i32(t2, t3, 0, 16);
1121 + tcg_gen_sextract_i32(t3, t3, 16, 16);
1122
1123 switch (optn2) {
1124 case MXU_OPTN2_WW: /* XRB.H*XRC.H == lop, XRB.L*XRC.L == rop */
1125 - tcg_gen_mul_tl(t3, t1, t3);
1126 - tcg_gen_mul_tl(t2, t0, t2);
1125 + tcg_gen_mul_i32(t3, t1, t3);
1126 + tcg_gen_mul_i32(t2, t0, t2);
1127 break;
1128 case MXU_OPTN2_LW: /* XRB.L*XRC.H == lop, XRB.L*XRC.L == rop */
1129 - tcg_gen_mul_tl(t3, t0, t3);
1130 - tcg_gen_mul_tl(t2, t0, t2);
1129 + tcg_gen_mul_i32(t3, t0, t3);
1130 + tcg_gen_mul_i32(t2, t0, t2);
1131 break;
1132 case MXU_OPTN2_HW: /* XRB.H*XRC.H == lop, XRB.H*XRC.L == rop */
1133 - tcg_gen_mul_tl(t3, t1, t3);
1134 - tcg_gen_mul_tl(t2, t1, t2);
1133 + tcg_gen_mul_i32(t3, t1, t3);
1134 + tcg_gen_mul_i32(t2, t1, t2);
1135 break;
1136 case MXU_OPTN2_XW: /* XRB.L*XRC.H == lop, XRB.H*XRC.L == rop */
1137 - tcg_gen_mul_tl(t3, t0, t3);
1138 - tcg_gen_mul_tl(t2, t1, t2);
1137 + tcg_gen_mul_i32(t3, t0, t3);
1138 + tcg_gen_mul_i32(t2, t1, t2);
1139 break;
1140 }
1141
1142 if (fractional) {
1143 - tcg_gen_shli_tl(t3, t3, 1);
1144 - tcg_gen_shli_tl(t2, t2, 1);
1143 + tcg_gen_shli_i32(t3, t3, 1);
1144 + tcg_gen_shli_i32(t2, t2, 1);
1145 }
1146 gen_load_mxu_gpr(t0, XRa);
1147 gen_load_mxu_gpr(t1, XRd);
1148
1149 switch (aptn2) {
1150 case MXU_APTN2_AA:
1151 - tcg_gen_add_tl(t3, t0, t3);
1152 - tcg_gen_add_tl(t2, t1, t2);
1151 + tcg_gen_add_i32(t3, t0, t3);
1152 + tcg_gen_add_i32(t2, t1, t2);
1153 break;
1154 case MXU_APTN2_AS:
1155 - tcg_gen_add_tl(t3, t0, t3);
1156 - tcg_gen_sub_tl(t2, t1, t2);
1155 + tcg_gen_add_i32(t3, t0, t3);
1156 + tcg_gen_sub_i32(t2, t1, t2);
1157 break;
1158 case MXU_APTN2_SA:
1159 - tcg_gen_sub_tl(t3, t0, t3);
1160 - tcg_gen_add_tl(t2, t1, t2);
1159 + tcg_gen_sub_i32(t3, t0, t3);
1160 + tcg_gen_add_i32(t2, t1, t2);
1161 break;
1162 case MXU_APTN2_SS:
1163 - tcg_gen_sub_tl(t3, t0, t3);
1164 - tcg_gen_sub_tl(t2, t1, t2);
1163 + tcg_gen_sub_i32(t3, t0, t3);
1164 + tcg_gen_sub_i32(t2, t1, t2);
1165 break;
1166 }
1167
1168 if (fractional) {
1169 TCGLabel *l_done = gen_new_label();
1170 - TCGv rounding = tcg_temp_new();
1170 + TCGv_i32 rounding = tcg_temp_new_i32();
1171
1172 - tcg_gen_andi_tl(rounding, mxu_CR, 0x2);
1173 - tcg_gen_brcondi_tl(TCG_COND_EQ, rounding, 0, l_done);
1172 + tcg_gen_andi_i32(rounding, mxu_CR, 0x2);
1173 + tcg_gen_brcondi_i32(TCG_COND_EQ, rounding, 0, l_done);
1174 if (packed_result) {
1175 TCGLabel *l_apply_bias_l = gen_new_label();
1176 TCGLabel *l_apply_bias_r = gen_new_label();
1177 TCGLabel *l_half_done = gen_new_label();
1178 - TCGv bias = tcg_temp_new();
1178 + TCGv_i32 bias = tcg_temp_new_i32();
1179
1180 /*
1181 * D16MACF supports unbiased rounding aka "bankers rounding",
1182 * "round to even", "convergent rounding"
1183 */
1184 - tcg_gen_andi_tl(bias, mxu_CR, 0x4);
1185 - tcg_gen_brcondi_tl(TCG_COND_NE, bias, 0, l_apply_bias_l);
1186 - tcg_gen_andi_tl(t0, t3, 0x1ffff);
1187 - tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0x8000, l_half_done);
1184 + tcg_gen_andi_i32(bias, mxu_CR, 0x4);
1185 + tcg_gen_brcondi_i32(TCG_COND_NE, bias, 0, l_apply_bias_l);
1186 + tcg_gen_andi_i32(t0, t3, 0x1ffff);
1187 + tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0x8000, l_half_done);
1188 gen_set_label(l_apply_bias_l);
1189 - tcg_gen_addi_tl(t3, t3, 0x8000);
1189 + tcg_gen_addi_i32(t3, t3, 0x8000);
1190 gen_set_label(l_half_done);
1191 - tcg_gen_brcondi_tl(TCG_COND_NE, bias, 0, l_apply_bias_r);
1192 - tcg_gen_andi_tl(t0, t2, 0x1ffff);
1193 - tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0x8000, l_done);
1191 + tcg_gen_brcondi_i32(TCG_COND_NE, bias, 0, l_apply_bias_r);
1192 + tcg_gen_andi_i32(t0, t2, 0x1ffff);
1193 + tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0x8000, l_done);
1194 gen_set_label(l_apply_bias_r);
1195 - tcg_gen_addi_tl(t2, t2, 0x8000);
1195 + tcg_gen_addi_i32(t2, t2, 0x8000);
1196 } else {
1197 /* D16MACE doesn't support unbiased rounding */
1198 - tcg_gen_addi_tl(t3, t3, 0x8000);
1199 - tcg_gen_addi_tl(t2, t2, 0x8000);
1198 + tcg_gen_addi_i32(t3, t3, 0x8000);
1199 + tcg_gen_addi_i32(t2, t2, 0x8000);
1200 }
1201 gen_set_label(l_done);
1202 }
@@ -1205,9 +1205,9 @@ static void gen_mxu_d16mac(DisasContext *ctx, bool fractional,
1205 gen_store_mxu_gpr(t3, XRa);
1206 gen_store_mxu_gpr(t2, XRd);
1207 } else {
1208 - tcg_gen_andi_tl(t3, t3, 0xffff0000);
1209 - tcg_gen_shri_tl(t2, t2, 16);
1210 - tcg_gen_or_tl(t3, t3, t2);
1208 + tcg_gen_andi_i32(t3, t3, 0xffff0000);
1209 + tcg_gen_shri_i32(t2, t2, 16);
1210 + tcg_gen_or_i32(t3, t3, t2);
1211 gen_store_mxu_gpr(t3, XRa);
1212 }
1213 }
@@ -1218,13 +1218,13 @@ static void gen_mxu_d16mac(DisasContext *ctx, bool fractional,
1218 */
1219 static void gen_mxu_d16madl(DisasContext *ctx)
1220 {
1221 - TCGv t0, t1, t2, t3;
1221 + TCGv_i32 t0, t1, t2, t3;
1222 uint32_t XRa, XRb, XRc, XRd, optn2, aptn2;
1223
1224 - t0 = tcg_temp_new();
1225 - t1 = tcg_temp_new();
1226 - t2 = tcg_temp_new();
1227 - t3 = tcg_temp_new();
1224 + t0 = tcg_temp_new_i32();
1225 + t1 = tcg_temp_new_i32();
1226 + t2 = tcg_temp_new_i32();
1227 + t3 = tcg_temp_new_i32();
1228
1229 XRa = extract32(ctx->opcode, 6, 4);
1230 XRb = extract32(ctx->opcode, 10, 4);
@@ -1234,60 +1234,60 @@ static void gen_mxu_d16madl(DisasContext *ctx)
1234 aptn2 = extract32(ctx->opcode, 24, 2);
1235
1236 gen_load_mxu_gpr(t1, XRb);
1237 - tcg_gen_sextract_tl(t0, t1, 0, 16);
1238 - tcg_gen_sextract_tl(t1, t1, 16, 16);
1237 + tcg_gen_sextract_i32(t0, t1, 0, 16);
1238 + tcg_gen_sextract_i32(t1, t1, 16, 16);
1239
1240 gen_load_mxu_gpr(t3, XRc);
1241 - tcg_gen_sextract_tl(t2, t3, 0, 16);
1242 - tcg_gen_sextract_tl(t3, t3, 16, 16);
1241 + tcg_gen_sextract_i32(t2, t3, 0, 16);
1242 + tcg_gen_sextract_i32(t3, t3, 16, 16);
1243
1244 switch (optn2) {
1245 case MXU_OPTN2_WW: /* XRB.H*XRC.H == lop, XRB.L*XRC.L == rop */
1246 - tcg_gen_mul_tl(t3, t1, t3);
1247 - tcg_gen_mul_tl(t2, t0, t2);
1246 + tcg_gen_mul_i32(t3, t1, t3);
1247 + tcg_gen_mul_i32(t2, t0, t2);
1248 break;
1249 case MXU_OPTN2_LW: /* XRB.L*XRC.H == lop, XRB.L*XRC.L == rop */
1250 - tcg_gen_mul_tl(t3, t0, t3);
1251 - tcg_gen_mul_tl(t2, t0, t2);
1250 + tcg_gen_mul_i32(t3, t0, t3);
1251 + tcg_gen_mul_i32(t2, t0, t2);
1252 break;
1253 case MXU_OPTN2_HW: /* XRB.H*XRC.H == lop, XRB.H*XRC.L == rop */
1254 - tcg_gen_mul_tl(t3, t1, t3);
1255 - tcg_gen_mul_tl(t2, t1, t2);
1254 + tcg_gen_mul_i32(t3, t1, t3);
1255 + tcg_gen_mul_i32(t2, t1, t2);
1256 break;
1257 case MXU_OPTN2_XW: /* XRB.L*XRC.H == lop, XRB.H*XRC.L == rop */
1258 - tcg_gen_mul_tl(t3, t0, t3);
1259 - tcg_gen_mul_tl(t2, t1, t2);
1258 + tcg_gen_mul_i32(t3, t0, t3);
1259 + tcg_gen_mul_i32(t2, t1, t2);
1260 break;
1261 }
1262 - tcg_gen_extract_tl(t2, t2, 0, 16);
1263 - tcg_gen_extract_tl(t3, t3, 0, 16);
1262 + tcg_gen_extract_i32(t2, t2, 0, 16);
1263 + tcg_gen_extract_i32(t3, t3, 0, 16);
1264
1265 gen_load_mxu_gpr(t1, XRa);
1266 - tcg_gen_extract_tl(t0, t1, 0, 16);
1267 - tcg_gen_extract_tl(t1, t1, 16, 16);
1266 + tcg_gen_extract_i32(t0, t1, 0, 16);
1267 + tcg_gen_extract_i32(t1, t1, 16, 16);
1268
1269 switch (aptn2) {
1270 case MXU_APTN2_AA:
1271 - tcg_gen_add_tl(t3, t1, t3);
1272 - tcg_gen_add_tl(t2, t0, t2);
1271 + tcg_gen_add_i32(t3, t1, t3);
1272 + tcg_gen_add_i32(t2, t0, t2);
1273 break;
1274 case MXU_APTN2_AS:
1275 - tcg_gen_add_tl(t3, t1, t3);
1276 - tcg_gen_sub_tl(t2, t0, t2);
1275 + tcg_gen_add_i32(t3, t1, t3);
1276 + tcg_gen_sub_i32(t2, t0, t2);
1277 break;
1278 case MXU_APTN2_SA:
1279 - tcg_gen_sub_tl(t3, t1, t3);
1280 - tcg_gen_add_tl(t2, t0, t2);
1279 + tcg_gen_sub_i32(t3, t1, t3);
1280 + tcg_gen_add_i32(t2, t0, t2);
1281 break;
1282 case MXU_APTN2_SS:
1283 - tcg_gen_sub_tl(t3, t1, t3);
1284 - tcg_gen_sub_tl(t2, t0, t2);
1283 + tcg_gen_sub_i32(t3, t1, t3);
1284 + tcg_gen_sub_i32(t2, t0, t2);
1285 break;
1286 }
1287
1288 - tcg_gen_andi_tl(t2, t2, 0xffff);
1289 - tcg_gen_shli_tl(t3, t3, 16);
1290 - tcg_gen_or_tl(mxu_gpr[XRd - 1], t3, t2);
1288 + tcg_gen_andi_i32(t2, t2, 0xffff);
1289 + tcg_gen_shli_i32(t3, t3, 16);
1290 + tcg_gen_or_i32(mxu_gpr[XRd - 1], t3, t2);
1291 }
1292
1293 /*
@@ -1296,11 +1296,11 @@ static void gen_mxu_d16madl(DisasContext *ctx)
1296 */
1297 static void gen_mxu_s16mad(DisasContext *ctx)
1298 {
1299 - TCGv t0, t1;
1299 + TCGv_i32 t0, t1;
1300 uint32_t XRa, XRb, XRc, XRd, optn2, aptn1, pad;
1301
1302 - t0 = tcg_temp_new();
1303 - t1 = tcg_temp_new();
1302 + t0 = tcg_temp_new_i32();
1303 + t1 = tcg_temp_new_i32();
1304
1305 XRa = extract32(ctx->opcode, 6, 4);
1306 XRb = extract32(ctx->opcode, 10, 4);
@@ -1319,32 +1319,32 @@ static void gen_mxu_s16mad(DisasContext *ctx)
1319
1320 switch (optn2) {
1321 case MXU_OPTN2_WW: /* XRB.H*XRC.H */
1322 - tcg_gen_sextract_tl(t0, t0, 16, 16);
1323 - tcg_gen_sextract_tl(t1, t1, 16, 16);
1322 + tcg_gen_sextract_i32(t0, t0, 16, 16);
1323 + tcg_gen_sextract_i32(t1, t1, 16, 16);
1324 break;
1325 case MXU_OPTN2_LW: /* XRB.L*XRC.L */
1326 - tcg_gen_sextract_tl(t0, t0, 0, 16);
1327 - tcg_gen_sextract_tl(t1, t1, 0, 16);
1326 + tcg_gen_sextract_i32(t0, t0, 0, 16);
1327 + tcg_gen_sextract_i32(t1, t1, 0, 16);
1328 break;
1329 case MXU_OPTN2_HW: /* XRB.H*XRC.L */
1330 - tcg_gen_sextract_tl(t0, t0, 16, 16);
1331 - tcg_gen_sextract_tl(t1, t1, 0, 16);
1330 + tcg_gen_sextract_i32(t0, t0, 16, 16);
1331 + tcg_gen_sextract_i32(t1, t1, 0, 16);
1332 break;
1333 case MXU_OPTN2_XW: /* XRB.L*XRC.H */
1334 - tcg_gen_sextract_tl(t0, t0, 0, 16);
1335 - tcg_gen_sextract_tl(t1, t1, 16, 16);
1334 + tcg_gen_sextract_i32(t0, t0, 0, 16);
1335 + tcg_gen_sextract_i32(t1, t1, 16, 16);
1336 break;
1337 }
1338 - tcg_gen_mul_tl(t0, t0, t1);
1338 + tcg_gen_mul_i32(t0, t0, t1);
1339
1340 gen_load_mxu_gpr(t1, XRa);
1341
1342 switch (aptn1) {
1343 case MXU_APTN1_A:
1344 - tcg_gen_add_tl(t1, t1, t0);
1344 + tcg_gen_add_i32(t1, t1, t0);
1345 break;
1346 case MXU_APTN1_S:
1347 - tcg_gen_sub_tl(t1, t1, t0);
1347 + tcg_gen_sub_i32(t1, t1, t0);
1348 break;
1349 }
1350
@@ -1361,17 +1361,17 @@ static void gen_mxu_s16mad(DisasContext *ctx)
1361 */
1362 static void gen_mxu_q8mul_mac(DisasContext *ctx, bool su, bool mac)
1363 {
1364 - TCGv t0, t1, t2, t3, t4, t5, t6, t7;
1364 + TCGv_i32 t0, t1, t2, t3, t4, t5, t6, t7;
1365 uint32_t XRa, XRb, XRc, XRd, aptn2;
1366
1367 - t0 = tcg_temp_new();
1368 - t1 = tcg_temp_new();
1369 - t2 = tcg_temp_new();
1370 - t3 = tcg_temp_new();
1371 - t4 = tcg_temp_new();
1372 - t5 = tcg_temp_new();
1373 - t6 = tcg_temp_new();
1374 - t7 = tcg_temp_new();
1367 + t0 = tcg_temp_new_i32();
1368 + t1 = tcg_temp_new_i32();
1369 + t2 = tcg_temp_new_i32();
1370 + t3 = tcg_temp_new_i32();
1371 + t4 = tcg_temp_new_i32();
1372 + t5 = tcg_temp_new_i32();
1373 + t6 = tcg_temp_new_i32();
1374 + t7 = tcg_temp_new_i32();
1375
1376 XRa = extract32(ctx->opcode, 6, 4);
1377 XRb = extract32(ctx->opcode, 10, 4);
@@ -1384,53 +1384,53 @@ static void gen_mxu_q8mul_mac(DisasContext *ctx, bool su, bool mac)
1384
1385 if (su) {
1386 /* Q8MULSU / Q8MACSU */
1387 - tcg_gen_sextract_tl(t0, t3, 0, 8);
1388 - tcg_gen_sextract_tl(t1, t3, 8, 8);
1389 - tcg_gen_sextract_tl(t2, t3, 16, 8);
1390 - tcg_gen_sextract_tl(t3, t3, 24, 8);
1387 + tcg_gen_sextract_i32(t0, t3, 0, 8);
1388 + tcg_gen_sextract_i32(t1, t3, 8, 8);
1389 + tcg_gen_sextract_i32(t2, t3, 16, 8);
1390 + tcg_gen_sextract_i32(t3, t3, 24, 8);
1391 } else {
1392 /* Q8MUL / Q8MAC */
1393 - tcg_gen_extract_tl(t0, t3, 0, 8);
1394 - tcg_gen_extract_tl(t1, t3, 8, 8);
1395 - tcg_gen_extract_tl(t2, t3, 16, 8);
1396 - tcg_gen_extract_tl(t3, t3, 24, 8);
1393 + tcg_gen_extract_i32(t0, t3, 0, 8);
1394 + tcg_gen_extract_i32(t1, t3, 8, 8);
1395 + tcg_gen_extract_i32(t2, t3, 16, 8);
1396 + tcg_gen_extract_i32(t3, t3, 24, 8);
1397 }
1398
1399 - tcg_gen_extract_tl(t4, t7, 0, 8);
1400 - tcg_gen_extract_tl(t5, t7, 8, 8);
1401 - tcg_gen_extract_tl(t6, t7, 16, 8);
1402 - tcg_gen_extract_tl(t7, t7, 24, 8);
1399 + tcg_gen_extract_i32(t4, t7, 0, 8);
1400 + tcg_gen_extract_i32(t5, t7, 8, 8);
1401 + tcg_gen_extract_i32(t6, t7, 16, 8);
1402 + tcg_gen_extract_i32(t7, t7, 24, 8);
1403
1404 - tcg_gen_mul_tl(t0, t0, t4);
1405 - tcg_gen_mul_tl(t1, t1, t5);
1406 - tcg_gen_mul_tl(t2, t2, t6);
1407 - tcg_gen_mul_tl(t3, t3, t7);
1404 + tcg_gen_mul_i32(t0, t0, t4);
1405 + tcg_gen_mul_i32(t1, t1, t5);
1406 + tcg_gen_mul_i32(t2, t2, t6);
1407 + tcg_gen_mul_i32(t3, t3, t7);
1408
1409 if (mac) {
1410 gen_load_mxu_gpr(t4, XRd);
1411 gen_load_mxu_gpr(t5, XRa);
1412 - tcg_gen_extract_tl(t6, t4, 0, 16);
1413 - tcg_gen_extract_tl(t7, t4, 16, 16);
1412 + tcg_gen_extract_i32(t6, t4, 0, 16);
1413 + tcg_gen_extract_i32(t7, t4, 16, 16);
1414 if (aptn2 & 1) {
1415 - tcg_gen_sub_tl(t0, t6, t0);
1416 - tcg_gen_sub_tl(t1, t7, t1);
1415 + tcg_gen_sub_i32(t0, t6, t0);
1416 + tcg_gen_sub_i32(t1, t7, t1);
1417 } else {
1418 - tcg_gen_add_tl(t0, t6, t0);
1419 - tcg_gen_add_tl(t1, t7, t1);
1418 + tcg_gen_add_i32(t0, t6, t0);
1419 + tcg_gen_add_i32(t1, t7, t1);
1420 }
1421 - tcg_gen_extract_tl(t6, t5, 0, 16);
1422 - tcg_gen_extract_tl(t7, t5, 16, 16);
1421 + tcg_gen_extract_i32(t6, t5, 0, 16);
1422 + tcg_gen_extract_i32(t7, t5, 16, 16);
1423 if (aptn2 & 2) {
1424 - tcg_gen_sub_tl(t2, t6, t2);
1425 - tcg_gen_sub_tl(t3, t7, t3);
1424 + tcg_gen_sub_i32(t2, t6, t2);
1425 + tcg_gen_sub_i32(t3, t7, t3);
1426 } else {
1427 - tcg_gen_add_tl(t2, t6, t2);
1428 - tcg_gen_add_tl(t3, t7, t3);
1427 + tcg_gen_add_i32(t2, t6, t2);
1428 + tcg_gen_add_i32(t3, t7, t3);
1429 }
1430 }
1431
1432 - tcg_gen_deposit_tl(t0, t0, t1, 16, 16);
1433 - tcg_gen_deposit_tl(t1, t2, t3, 16, 16);
1432 + tcg_gen_deposit_i32(t0, t0, t1, 16, 16);
1433 + tcg_gen_deposit_i32(t1, t2, t3, 16, 16);
1434
1435 gen_store_mxu_gpr(t0, XRd);
1436 gen_store_mxu_gpr(t1, XRa);
@@ -1443,17 +1443,17 @@ static void gen_mxu_q8mul_mac(DisasContext *ctx, bool su, bool mac)
1443 */
1444 static void gen_mxu_q8madl(DisasContext *ctx)
1445 {
1446 - TCGv t0, t1, t2, t3, t4, t5, t6, t7;
1446 + TCGv_i32 t0, t1, t2, t3, t4, t5, t6, t7;
1447 uint32_t XRa, XRb, XRc, XRd, aptn2;
1448
1449 - t0 = tcg_temp_new();
1450 - t1 = tcg_temp_new();
1451 - t2 = tcg_temp_new();
1452 - t3 = tcg_temp_new();
1453 - t4 = tcg_temp_new();
1454 - t5 = tcg_temp_new();
1455 - t6 = tcg_temp_new();
1456 - t7 = tcg_temp_new();
1449 + t0 = tcg_temp_new_i32();
1450 + t1 = tcg_temp_new_i32();
1451 + t2 = tcg_temp_new_i32();
1452 + t3 = tcg_temp_new_i32();
1453 + t4 = tcg_temp_new_i32();
1454 + t5 = tcg_temp_new_i32();
1455 + t6 = tcg_temp_new_i32();
1456 + t7 = tcg_temp_new_i32();
1457
1458 XRa = extract32(ctx->opcode, 6, 4);
1459 XRb = extract32(ctx->opcode, 10, 4);
@@ -1464,45 +1464,45 @@ static void gen_mxu_q8madl(DisasContext *ctx)
1464 gen_load_mxu_gpr(t3, XRb);
1465 gen_load_mxu_gpr(t7, XRc);
1466
1467 - tcg_gen_extract_tl(t0, t3, 0, 8);
1468 - tcg_gen_extract_tl(t1, t3, 8, 8);
1469 - tcg_gen_extract_tl(t2, t3, 16, 8);
1470 - tcg_gen_extract_tl(t3, t3, 24, 8);
1467 + tcg_gen_extract_i32(t0, t3, 0, 8);
1468 + tcg_gen_extract_i32(t1, t3, 8, 8);
1469 + tcg_gen_extract_i32(t2, t3, 16, 8);
1470 + tcg_gen_extract_i32(t3, t3, 24, 8);
1471
1472 - tcg_gen_extract_tl(t4, t7, 0, 8);
1473 - tcg_gen_extract_tl(t5, t7, 8, 8);
1474 - tcg_gen_extract_tl(t6, t7, 16, 8);
1475 - tcg_gen_extract_tl(t7, t7, 24, 8);
1472 + tcg_gen_extract_i32(t4, t7, 0, 8);
1473 + tcg_gen_extract_i32(t5, t7, 8, 8);
1474 + tcg_gen_extract_i32(t6, t7, 16, 8);
1475 + tcg_gen_extract_i32(t7, t7, 24, 8);
1476
1477 - tcg_gen_mul_tl(t0, t0, t4);
1478 - tcg_gen_mul_tl(t1, t1, t5);
1479 - tcg_gen_mul_tl(t2, t2, t6);
1480 - tcg_gen_mul_tl(t3, t3, t7);
1477 + tcg_gen_mul_i32(t0, t0, t4);
1478 + tcg_gen_mul_i32(t1, t1, t5);
1479 + tcg_gen_mul_i32(t2, t2, t6);
1480 + tcg_gen_mul_i32(t3, t3, t7);
1481
1482 gen_load_mxu_gpr(t4, XRa);
1483 - tcg_gen_extract_tl(t6, t4, 0, 8);
1484 - tcg_gen_extract_tl(t7, t4, 8, 8);
1483 + tcg_gen_extract_i32(t6, t4, 0, 8);
1484 + tcg_gen_extract_i32(t7, t4, 8, 8);
1485 if (aptn2 & 1) {
1486 - tcg_gen_sub_tl(t0, t6, t0);
1487 - tcg_gen_sub_tl(t1, t7, t1);
1486 + tcg_gen_sub_i32(t0, t6, t0);
1487 + tcg_gen_sub_i32(t1, t7, t1);
1488 } else {
1489 - tcg_gen_add_tl(t0, t6, t0);
1490 - tcg_gen_add_tl(t1, t7, t1);
1489 + tcg_gen_add_i32(t0, t6, t0);
1490 + tcg_gen_add_i32(t1, t7, t1);
1491 }
1492 - tcg_gen_extract_tl(t6, t4, 16, 8);
1493 - tcg_gen_extract_tl(t7, t4, 24, 8);
1492 + tcg_gen_extract_i32(t6, t4, 16, 8);
1493 + tcg_gen_extract_i32(t7, t4, 24, 8);
1494 if (aptn2 & 2) {
1495 - tcg_gen_sub_tl(t2, t6, t2);
1496 - tcg_gen_sub_tl(t3, t7, t3);
1495 + tcg_gen_sub_i32(t2, t6, t2);
1496 + tcg_gen_sub_i32(t3, t7, t3);
1497 } else {
1498 - tcg_gen_add_tl(t2, t6, t2);
1499 - tcg_gen_add_tl(t3, t7, t3);
1498 + tcg_gen_add_i32(t2, t6, t2);
1499 + tcg_gen_add_i32(t3, t7, t3);
1500 }
1501
1502 - tcg_gen_andi_tl(t5, t0, 0xff);
1503 - tcg_gen_deposit_tl(t5, t5, t1, 8, 8);
1504 - tcg_gen_deposit_tl(t5, t5, t2, 16, 8);
1505 - tcg_gen_deposit_tl(t5, t5, t3, 24, 8);
1502 + tcg_gen_andi_i32(t5, t0, 0xff);
1503 + tcg_gen_deposit_i32(t5, t5, t1, 8, 8);
1504 + tcg_gen_deposit_i32(t5, t5, t2, 16, 8);
1505 + tcg_gen_deposit_i32(t5, t5, t3, 24, 8);
1506
1507 gen_store_mxu_gpr(t5, XRd);
1508 }
@@ -1518,21 +1518,21 @@ static void gen_mxu_q8madl(DisasContext *ctx)
1518 */
1519 static void gen_mxu_s32ldxx(DisasContext *ctx, bool reversed, bool postinc)
1520 {
1521 - TCGv t0, t1;
1521 + TCGv_i32 t0, t1;
1522 uint32_t XRa, Rb, s12;
1523
1524 - t0 = tcg_temp_new();
1525 - t1 = tcg_temp_new();
1524 + t0 = tcg_temp_new_i32();
1525 + t1 = tcg_temp_new_i32();
1526
1527 XRa = extract32(ctx->opcode, 6, 4);
1528 s12 = sextract32(ctx->opcode, 10, 10);
1529 Rb = extract32(ctx->opcode, 21, 5);
1530
1531 gen_load_gpr(t0, Rb);
1532 - tcg_gen_movi_tl(t1, s12 * 4);
1533 - tcg_gen_add_tl(t0, t0, t1);
1532 + tcg_gen_movi_i32(t1, s12 * 4);
1533 + tcg_gen_add_i32(t0, t0, t1);
1534
1535 - tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx,
1535 + tcg_gen_qemu_ld_i32(t1, t0, ctx->mem_idx,
1536 MO_SL | mo_endian_rev(ctx, reversed) |
1537 ctx->default_tcg_memop_mask);
1538 gen_store_mxu_gpr(t1, XRa);
@@ -1553,22 +1553,22 @@ static void gen_mxu_s32ldxx(DisasContext *ctx, bool reversed, bool postinc)
1553 */
1554 static void gen_mxu_s32stxx(DisasContext *ctx, bool reversed, bool postinc)
1555 {
1556 - TCGv t0, t1;
1556 + TCGv_i32 t0, t1;
1557 uint32_t XRa, Rb, s12;
1558
1559 - t0 = tcg_temp_new();
1560 - t1 = tcg_temp_new();
1559 + t0 = tcg_temp_new_i32();
1560 + t1 = tcg_temp_new_i32();
1561
1562 XRa = extract32(ctx->opcode, 6, 4);
1563 s12 = sextract32(ctx->opcode, 10, 10);
1564 Rb = extract32(ctx->opcode, 21, 5);
1565
1566 gen_load_gpr(t0, Rb);
1567 - tcg_gen_movi_tl(t1, s12 * 4);
1568 - tcg_gen_add_tl(t0, t0, t1);
1567 + tcg_gen_movi_i32(t1, s12 * 4);
1568 + tcg_gen_add_i32(t0, t0, t1);
1569
1570 gen_load_mxu_gpr(t1, XRa);
1571 - tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx,
1571 + tcg_gen_qemu_st_i32(t1, t0, ctx->mem_idx,
1572 MO_SL | mo_endian_rev(ctx, reversed) |
1573 ctx->default_tcg_memop_mask);
1574
@@ -1589,11 +1589,11 @@ static void gen_mxu_s32stxx(DisasContext *ctx, bool reversed, bool postinc)
1589 static void gen_mxu_s32ldxvx(DisasContext *ctx, bool reversed,
1590 bool postinc, uint32_t strd2)
1591 {
1592 - TCGv t0, t1;
1592 + TCGv_i32 t0, t1;
1593 uint32_t XRa, Rb, Rc;
1594
1595 - t0 = tcg_temp_new();
1596 - t1 = tcg_temp_new();
1595 + t0 = tcg_temp_new_i32();
1596 + t1 = tcg_temp_new_i32();
1597
1598 XRa = extract32(ctx->opcode, 6, 4);
1599 Rc = extract32(ctx->opcode, 16, 5);
@@ -1601,10 +1601,10 @@ static void gen_mxu_s32ldxvx(DisasContext *ctx, bool reversed,
1601
1602 gen_load_gpr(t0, Rb);
1603 gen_load_gpr(t1, Rc);
1604 - tcg_gen_shli_tl(t1, t1, strd2);
1605 - tcg_gen_add_tl(t0, t0, t1);
1604 + tcg_gen_shli_i32(t1, t1, strd2);
1605 + tcg_gen_add_i32(t0, t0, t1);
1606
1607 - tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx,
1607 + tcg_gen_qemu_ld_i32(t1, t0, ctx->mem_idx,
1608 MO_SL | mo_endian_rev(ctx, reversed) |
1609 ctx->default_tcg_memop_mask);
1610 gen_store_mxu_gpr(t1, XRa);
@@ -1627,11 +1627,11 @@ static void gen_mxu_s32ldxvx(DisasContext *ctx, bool reversed,
1627 */
1628 static void gen_mxu_lxx(DisasContext *ctx, uint32_t strd2, MemOp mop)
1629 {
1630 - TCGv t0, t1;
1630 + TCGv_i32 t0, t1;
1631 uint32_t Ra, Rb, Rc;
1632
1633 - t0 = tcg_temp_new();
1634 - t1 = tcg_temp_new();
1633 + t0 = tcg_temp_new_i32();
1634 + t1 = tcg_temp_new_i32();
1635
1636 Ra = extract32(ctx->opcode, 11, 5);
1637 Rc = extract32(ctx->opcode, 16, 5);
@@ -1639,10 +1639,10 @@ static void gen_mxu_lxx(DisasContext *ctx, uint32_t strd2, MemOp mop)
1639
1640 gen_load_gpr(t0, Rb);
1641 gen_load_gpr(t1, Rc);
1642 - tcg_gen_shli_tl(t1, t1, strd2);
1643 - tcg_gen_add_tl(t0, t0, t1);
1642 + tcg_gen_shli_i32(t1, t1, strd2);
1643 + tcg_gen_add_i32(t0, t0, t1);
1644
1645 - tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, mop | ctx->default_tcg_memop_mask);
1645 + tcg_gen_qemu_ld_i32(t1, t0, ctx->mem_idx, mop | ctx->default_tcg_memop_mask);
1646 gen_store_gpr(t1, Ra);
1647 }
1648
@@ -1658,11 +1658,11 @@ static void gen_mxu_lxx(DisasContext *ctx, uint32_t strd2, MemOp mop)
1658 static void gen_mxu_s32stxvx(DisasContext *ctx, bool reversed,
1659 bool postinc, uint32_t strd2)
1660 {
1661 - TCGv t0, t1;
1661 + TCGv_i32 t0, t1;
1662 uint32_t XRa, Rb, Rc;
1663
1664 - t0 = tcg_temp_new();
1665 - t1 = tcg_temp_new();
1664 + t0 = tcg_temp_new_i32();
1665 + t1 = tcg_temp_new_i32();
1666
1667 XRa = extract32(ctx->opcode, 6, 4);
1668 Rc = extract32(ctx->opcode, 16, 5);
@@ -1670,11 +1670,11 @@ static void gen_mxu_s32stxvx(DisasContext *ctx, bool reversed,
1670
1671 gen_load_gpr(t0, Rb);
1672 gen_load_gpr(t1, Rc);
1673 - tcg_gen_shli_tl(t1, t1, strd2);
1674 - tcg_gen_add_tl(t0, t0, t1);
1673 + tcg_gen_shli_i32(t1, t1, strd2);
1674 + tcg_gen_add_i32(t0, t0, t1);
1675
1676 gen_load_mxu_gpr(t1, XRa);
1677 - tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx,
1677 + tcg_gen_qemu_st_i32(t1, t0, ctx->mem_idx,
1678 MO_SL | mo_endian_rev(ctx, reversed) |
1679 ctx->default_tcg_memop_mask);
1680
@@ -1859,23 +1859,23 @@ static void gen_mxu_d32sxx(DisasContext *ctx, bool right, bool arithmetic)
1859 XRd = extract32(ctx->opcode, 18, 4);
1860 sft4 = extract32(ctx->opcode, 22, 4);
1861
1862 - TCGv t0 = tcg_temp_new();
1863 - TCGv t1 = tcg_temp_new();
1862 + TCGv_i32 t0 = tcg_temp_new_i32();
1863 + TCGv_i32 t1 = tcg_temp_new_i32();
1864
1865 gen_load_mxu_gpr(t0, XRb);
1866 gen_load_mxu_gpr(t1, XRc);
1867
1868 if (right) {
1869 if (arithmetic) {
1870 - tcg_gen_sari_tl(t0, t0, sft4);
1871 - tcg_gen_sari_tl(t1, t1, sft4);
1870 + tcg_gen_sari_i32(t0, t0, sft4);
1871 + tcg_gen_sari_i32(t1, t1, sft4);
1872 } else {
1873 - tcg_gen_shri_tl(t0, t0, sft4);
1874 - tcg_gen_shri_tl(t1, t1, sft4);
1873 + tcg_gen_shri_i32(t0, t0, sft4);
1874 + tcg_gen_shri_i32(t1, t1, sft4);
1875 }
1876 } else {
1877 - tcg_gen_shli_tl(t0, t0, sft4);
1878 - tcg_gen_shli_tl(t1, t1, sft4);
1877 + tcg_gen_shli_i32(t0, t0, sft4);
1878 + tcg_gen_shli_i32(t1, t1, sft4);
1879 }
1880 gen_store_mxu_gpr(t0, XRa);
1881 gen_store_mxu_gpr(t1, XRd);
@@ -1900,26 +1900,26 @@ static void gen_mxu_d32sxxv(DisasContext *ctx, bool right, bool arithmetic)
1900 XRd = extract32(ctx->opcode, 14, 4);
1901 rs = extract32(ctx->opcode, 21, 5);
1902
1903 - TCGv t0 = tcg_temp_new();
1904 - TCGv t1 = tcg_temp_new();
1905 - TCGv t2 = tcg_temp_new();
1903 + TCGv_i32 t0 = tcg_temp_new_i32();
1904 + TCGv_i32 t1 = tcg_temp_new_i32();
1905 + TCGv_i32 t2 = tcg_temp_new_i32();
1906
1907 gen_load_mxu_gpr(t0, XRa);
1908 gen_load_mxu_gpr(t1, XRd);
1909 gen_load_gpr(t2, rs);
1910 - tcg_gen_andi_tl(t2, t2, 0x0f);
1910 + tcg_gen_andi_i32(t2, t2, 0x0f);
1911
1912 if (right) {
1913 if (arithmetic) {
1914 - tcg_gen_sar_tl(t0, t0, t2);
1915 - tcg_gen_sar_tl(t1, t1, t2);
1914 + tcg_gen_sar_i32(t0, t0, t2);
1915 + tcg_gen_sar_i32(t1, t1, t2);
1916 } else {
1917 - tcg_gen_shr_tl(t0, t0, t2);
1918 - tcg_gen_shr_tl(t1, t1, t2);
1917 + tcg_gen_shr_i32(t0, t0, t2);
1918 + tcg_gen_shr_i32(t1, t1, t2);
1919 }
1920 } else {
1921 - tcg_gen_shl_tl(t0, t0, t2);
1922 - tcg_gen_shl_tl(t1, t1, t2);
1921 + tcg_gen_shl_i32(t0, t0, t2);
1922 + tcg_gen_shl_i32(t1, t1, t2);
1923 }
1924 gen_store_mxu_gpr(t0, XRa);
1925 gen_store_mxu_gpr(t1, XRd);
@@ -1946,23 +1946,23 @@ static void gen_mxu_d32sarl(DisasContext *ctx, bool sarw)
1946 if (unlikely(XRa == 0)) {
1947 /* destination is zero register -> do nothing */
1948 } else {
1949 - TCGv t0 = tcg_temp_new();
1950 - TCGv t1 = tcg_temp_new();
1951 - TCGv t2 = tcg_temp_new();
1949 + TCGv_i32 t0 = tcg_temp_new_i32();
1950 + TCGv_i32 t1 = tcg_temp_new_i32();
1951 + TCGv_i32 t2 = tcg_temp_new_i32();
1952
1953 if (!sarw) {
1954 /* Make SFT4 from rb field */
1955 - tcg_gen_movi_tl(t2, rb >> 1);
1955 + tcg_gen_movi_i32(t2, rb >> 1);
1956 } else {
1957 gen_load_gpr(t2, rb);
1958 - tcg_gen_andi_tl(t2, t2, 0x0f);
1958 + tcg_gen_andi_i32(t2, t2, 0x0f);
1959 }
1960 gen_load_mxu_gpr(t0, XRb);
1961 gen_load_mxu_gpr(t1, XRc);
1962 - tcg_gen_sar_tl(t0, t0, t2);
1963 - tcg_gen_sar_tl(t1, t1, t2);
1964 - tcg_gen_extract_tl(t2, t1, 0, 16);
1965 - tcg_gen_deposit_tl(t2, t2, t0, 16, 16);
1962 + tcg_gen_sar_i32(t0, t0, t2);
1963 + tcg_gen_sar_i32(t1, t1, t2);
1964 + tcg_gen_extract_i32(t2, t1, 0, 16);
1965 + tcg_gen_deposit_i32(t2, t2, t0, 16, 16);
1966 gen_store_mxu_gpr(t2, XRa);
1967 }
1968 }
@@ -1988,46 +1988,46 @@ static void gen_mxu_q16sxx(DisasContext *ctx, bool right, bool arithmetic)
1988 XRd = extract32(ctx->opcode, 18, 4);
1989 sft4 = extract32(ctx->opcode, 22, 4);
1990
1991 - TCGv t0 = tcg_temp_new();
1992 - TCGv t1 = tcg_temp_new();
1993 - TCGv t2 = tcg_temp_new();
1994 - TCGv t3 = tcg_temp_new();
1991 + TCGv_i32 t0 = tcg_temp_new_i32();
1992 + TCGv_i32 t1 = tcg_temp_new_i32();
1993 + TCGv_i32 t2 = tcg_temp_new_i32();
1994 + TCGv_i32 t3 = tcg_temp_new_i32();
1995
1996 gen_load_mxu_gpr(t0, XRb);
1997 gen_load_mxu_gpr(t2, XRc);
1998
1999 if (arithmetic) {
2000 - tcg_gen_sextract_tl(t1, t0, 16, 16);
2001 - tcg_gen_sextract_tl(t0, t0, 0, 16);
2002 - tcg_gen_sextract_tl(t3, t2, 16, 16);
2003 - tcg_gen_sextract_tl(t2, t2, 0, 16);
2000 + tcg_gen_sextract_i32(t1, t0, 16, 16);
2001 + tcg_gen_sextract_i32(t0, t0, 0, 16);
2002 + tcg_gen_sextract_i32(t3, t2, 16, 16);
2003 + tcg_gen_sextract_i32(t2, t2, 0, 16);
2004 } else {
2005 - tcg_gen_extract_tl(t1, t0, 16, 16);
2006 - tcg_gen_extract_tl(t0, t0, 0, 16);
2007 - tcg_gen_extract_tl(t3, t2, 16, 16);
2008 - tcg_gen_extract_tl(t2, t2, 0, 16);
2005 + tcg_gen_extract_i32(t1, t0, 16, 16);
2006 + tcg_gen_extract_i32(t0, t0, 0, 16);
2007 + tcg_gen_extract_i32(t3, t2, 16, 16);
2008 + tcg_gen_extract_i32(t2, t2, 0, 16);
2009 }
2010
2011 if (right) {
2012 if (arithmetic) {
2013 - tcg_gen_sari_tl(t0, t0, sft4);
2014 - tcg_gen_sari_tl(t1, t1, sft4);
2015 - tcg_gen_sari_tl(t2, t2, sft4);
2016 - tcg_gen_sari_tl(t3, t3, sft4);
2013 + tcg_gen_sari_i32(t0, t0, sft4);
2014 + tcg_gen_sari_i32(t1, t1, sft4);
2015 + tcg_gen_sari_i32(t2, t2, sft4);
2016 + tcg_gen_sari_i32(t3, t3, sft4);
2017 } else {
2018 - tcg_gen_shri_tl(t0, t0, sft4);
2019 - tcg_gen_shri_tl(t1, t1, sft4);
2020 - tcg_gen_shri_tl(t2, t2, sft4);
2021 - tcg_gen_shri_tl(t3, t3, sft4);
2018 + tcg_gen_shri_i32(t0, t0, sft4);
2019 + tcg_gen_shri_i32(t1, t1, sft4);
2020 + tcg_gen_shri_i32(t2, t2, sft4);
2021 + tcg_gen_shri_i32(t3, t3, sft4);
2022 }
2023 } else {
2024 - tcg_gen_shli_tl(t0, t0, sft4);
2025 - tcg_gen_shli_tl(t1, t1, sft4);
2026 - tcg_gen_shli_tl(t2, t2, sft4);
2027 - tcg_gen_shli_tl(t3, t3, sft4);
2024 + tcg_gen_shli_i32(t0, t0, sft4);
2025 + tcg_gen_shli_i32(t1, t1, sft4);
2026 + tcg_gen_shli_i32(t2, t2, sft4);
2027 + tcg_gen_shli_i32(t3, t3, sft4);
2028 }
2029 - tcg_gen_deposit_tl(t0, t0, t1, 16, 16);
2030 - tcg_gen_deposit_tl(t2, t2, t3, 16, 16);
2029 + tcg_gen_deposit_i32(t0, t0, t1, 16, 16);
2030 + tcg_gen_deposit_i32(t2, t2, t3, 16, 16);
2031
2032 gen_store_mxu_gpr(t0, XRa);
2033 gen_store_mxu_gpr(t2, XRd);
@@ -2052,50 +2052,50 @@ static void gen_mxu_q16sxxv(DisasContext *ctx, bool right, bool arithmetic)
2052 XRd = extract32(ctx->opcode, 14, 4);
2053 rs = extract32(ctx->opcode, 21, 5);
2054
2055 - TCGv t0 = tcg_temp_new();
2056 - TCGv t1 = tcg_temp_new();
2057 - TCGv t2 = tcg_temp_new();
2058 - TCGv t3 = tcg_temp_new();
2059 - TCGv t5 = tcg_temp_new();
2055 + TCGv_i32 t0 = tcg_temp_new_i32();
2056 + TCGv_i32 t1 = tcg_temp_new_i32();
2057 + TCGv_i32 t2 = tcg_temp_new_i32();
2058 + TCGv_i32 t3 = tcg_temp_new_i32();
2059 + TCGv_i32 t5 = tcg_temp_new_i32();
2060
2061 gen_load_mxu_gpr(t0, XRa);
2062 gen_load_mxu_gpr(t2, XRd);
2063 gen_load_gpr(t5, rs);
2064 - tcg_gen_andi_tl(t5, t5, 0x0f);
2064 + tcg_gen_andi_i32(t5, t5, 0x0f);
2065
2066
2067 if (arithmetic) {
2068 - tcg_gen_sextract_tl(t1, t0, 16, 16);
2069 - tcg_gen_sextract_tl(t0, t0, 0, 16);
2070 - tcg_gen_sextract_tl(t3, t2, 16, 16);
2071 - tcg_gen_sextract_tl(t2, t2, 0, 16);
2068 + tcg_gen_sextract_i32(t1, t0, 16, 16);
2069 + tcg_gen_sextract_i32(t0, t0, 0, 16);
2070 + tcg_gen_sextract_i32(t3, t2, 16, 16);
2071 + tcg_gen_sextract_i32(t2, t2, 0, 16);
2072 } else {
2073 - tcg_gen_extract_tl(t1, t0, 16, 16);
2074 - tcg_gen_extract_tl(t0, t0, 0, 16);
2075 - tcg_gen_extract_tl(t3, t2, 16, 16);
2076 - tcg_gen_extract_tl(t2, t2, 0, 16);
2073 + tcg_gen_extract_i32(t1, t0, 16, 16);
2074 + tcg_gen_extract_i32(t0, t0, 0, 16);
2075 + tcg_gen_extract_i32(t3, t2, 16, 16);
2076 + tcg_gen_extract_i32(t2, t2, 0, 16);
2077 }
2078
2079 if (right) {
2080 if (arithmetic) {
2081 - tcg_gen_sar_tl(t0, t0, t5);
2082 - tcg_gen_sar_tl(t1, t1, t5);
2083 - tcg_gen_sar_tl(t2, t2, t5);
2084 - tcg_gen_sar_tl(t3, t3, t5);
2081 + tcg_gen_sar_i32(t0, t0, t5);
2082 + tcg_gen_sar_i32(t1, t1, t5);
2083 + tcg_gen_sar_i32(t2, t2, t5);
2084 + tcg_gen_sar_i32(t3, t3, t5);
2085 } else {
2086 - tcg_gen_shr_tl(t0, t0, t5);
2087 - tcg_gen_shr_tl(t1, t1, t5);
2088 - tcg_gen_shr_tl(t2, t2, t5);
2089 - tcg_gen_shr_tl(t3, t3, t5);
2086 + tcg_gen_shr_i32(t0, t0, t5);
2087 + tcg_gen_shr_i32(t1, t1, t5);
2088 + tcg_gen_shr_i32(t2, t2, t5);
2089 + tcg_gen_shr_i32(t3, t3, t5);
2090 }
2091 } else {
2092 - tcg_gen_shl_tl(t0, t0, t5);
2093 - tcg_gen_shl_tl(t1, t1, t5);
2094 - tcg_gen_shl_tl(t2, t2, t5);
2095 - tcg_gen_shl_tl(t3, t3, t5);
2092 + tcg_gen_shl_i32(t0, t0, t5);
2093 + tcg_gen_shl_i32(t1, t1, t5);
2094 + tcg_gen_shl_i32(t2, t2, t5);
2095 + tcg_gen_shl_i32(t3, t3, t5);
2096 }
2097 - tcg_gen_deposit_tl(t0, t0, t1, 16, 16);
2098 - tcg_gen_deposit_tl(t2, t2, t3, 16, 16);
2097 + tcg_gen_deposit_i32(t0, t0, t1, 16, 16);
2098 + tcg_gen_deposit_i32(t2, t2, t3, 16, 16);
2099
2100 gen_store_mxu_gpr(t0, XRa);
2101 gen_store_mxu_gpr(t2, XRd);
@@ -2195,9 +2195,9 @@ static void gen_mxu_D16MAX_D16MIN(DisasContext *ctx)
2195 /* exactly one operand is zero register - find which one is not...*/
2196 uint32_t XRx = XRb ? XRb : XRc;
2197 /* ...and do half-word-wise max/min with one operand 0 */
2198 - TCGv_i32 t0 = tcg_temp_new();
2198 + TCGv_i32 t0 = tcg_temp_new_i32();
2199 TCGv_i32 t1 = tcg_constant_i32(0);
2200 - TCGv_i32 t2 = tcg_temp_new();
2200 + TCGv_i32 t2 = tcg_temp_new_i32();
2201
2202 /* the left half-word first */
2203 tcg_gen_andi_i32(t0, mxu_gpr[XRx - 1], 0xFFFF0000);
@@ -2226,9 +2226,9 @@ static void gen_mxu_D16MAX_D16MIN(DisasContext *ctx)
2226 tcg_gen_mov_i32(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1]);
2227 } else {
2228 /* the most general case */
2229 - TCGv_i32 t0 = tcg_temp_new();
2230 - TCGv_i32 t1 = tcg_temp_new();
2231 - TCGv_i32 t2 = tcg_temp_new();
2229 + TCGv_i32 t0 = tcg_temp_new_i32();
2230 + TCGv_i32 t1 = tcg_temp_new_i32();
2231 + TCGv_i32 t2 = tcg_temp_new_i32();
2232
2233 /* the left half-word first */
2234 tcg_gen_andi_i32(t0, mxu_gpr[XRb - 1], 0xFFFF0000);
@@ -2288,9 +2288,9 @@ static void gen_mxu_Q8MAX_Q8MIN(DisasContext *ctx)
2288 /* exactly one operand is zero register - make it be the first...*/
2289 uint32_t XRx = XRb ? XRb : XRc;
2290 /* ...and do byte-wise max/min with one operand 0 */
2291 - TCGv_i32 t0 = tcg_temp_new();
2291 + TCGv_i32 t0 = tcg_temp_new_i32();
2292 TCGv_i32 t1 = tcg_constant_i32(0);
2293 - TCGv_i32 t2 = tcg_temp_new();
2293 + TCGv_i32 t2 = tcg_temp_new_i32();
2294 int32_t i;
2295
2296 /* the leftmost byte (byte 3) first */
@@ -2324,9 +2324,9 @@ static void gen_mxu_Q8MAX_Q8MIN(DisasContext *ctx)
2324 tcg_gen_mov_i32(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1]);
2325 } else {
2326 /* the most general case */
2327 - TCGv_i32 t0 = tcg_temp_new();
2328 - TCGv_i32 t1 = tcg_temp_new();
2329 - TCGv_i32 t2 = tcg_temp_new();
2327 + TCGv_i32 t0 = tcg_temp_new_i32();
2328 + TCGv_i32 t1 = tcg_temp_new_i32();
2329 + TCGv_i32 t2 = tcg_temp_new_i32();
2330 int32_t i;
2331
2332 /* the leftmost bytes (bytes 3) first */
@@ -2387,32 +2387,32 @@ static void gen_mxu_q8slt(DisasContext *ctx, bool sltu)
2387 /* destination is zero register -> do nothing */
2388 } else if (unlikely((XRb == 0) && (XRc == 0))) {
2389 /* both operands zero registers -> just set destination to zero */
2390 - tcg_gen_movi_tl(mxu_gpr[XRa - 1], 0);
2390 + tcg_gen_movi_i32(mxu_gpr[XRa - 1], 0);
2391 } else if (unlikely(XRb == XRc)) {
2392 /* both operands same registers -> just set destination to zero */
2393 - tcg_gen_movi_tl(mxu_gpr[XRa - 1], 0);
2393 + tcg_gen_movi_i32(mxu_gpr[XRa - 1], 0);
2394 } else {
2395 /* the most general case */
2396 - TCGv t0 = tcg_temp_new();
2397 - TCGv t1 = tcg_temp_new();
2398 - TCGv t2 = tcg_temp_new();
2399 - TCGv t3 = tcg_temp_new();
2400 - TCGv t4 = tcg_temp_new();
2396 + TCGv_i32 t0 = tcg_temp_new_i32();
2397 + TCGv_i32 t1 = tcg_temp_new_i32();
2398 + TCGv_i32 t2 = tcg_temp_new_i32();
2399 + TCGv_i32 t3 = tcg_temp_new_i32();
2400 + TCGv_i32 t4 = tcg_temp_new_i32();
2401
2402 gen_load_mxu_gpr(t3, XRb);
2403 gen_load_mxu_gpr(t4, XRc);
2404 - tcg_gen_movi_tl(t2, 0);
2404 + tcg_gen_movi_i32(t2, 0);
2405
2406 for (int i = 0; i < 4; i++) {
2407 if (sltu) {
2408 - tcg_gen_extract_tl(t0, t3, 8 * i, 8);
2409 - tcg_gen_extract_tl(t1, t4, 8 * i, 8);
2408 + tcg_gen_extract_i32(t0, t3, 8 * i, 8);
2409 + tcg_gen_extract_i32(t1, t4, 8 * i, 8);
2410 } else {
2411 - tcg_gen_sextract_tl(t0, t3, 8 * i, 8);
2412 - tcg_gen_sextract_tl(t1, t4, 8 * i, 8);
2411 + tcg_gen_sextract_i32(t0, t3, 8 * i, 8);
2412 + tcg_gen_sextract_i32(t1, t4, 8 * i, 8);
2413 }
2414 - tcg_gen_setcond_tl(TCG_COND_LT, t0, t0, t1);
2415 - tcg_gen_deposit_tl(t2, t2, t0, 8 * i, 8);
2414 + tcg_gen_setcond_i32(TCG_COND_LT, t0, t0, t1);
2415 + tcg_gen_deposit_i32(t2, t2, t0, 8 * i, 8);
2416 }
2417 gen_store_mxu_gpr(t2, XRa);
2418 }
@@ -2438,18 +2438,18 @@ static void gen_mxu_S32SLT(DisasContext *ctx)
2438 /* destination is zero register -> do nothing */
2439 } else if (unlikely((XRb == 0) && (XRc == 0))) {
2440 /* both operands zero registers -> just set destination to zero */
2441 - tcg_gen_movi_tl(mxu_gpr[XRa - 1], 0);
2441 + tcg_gen_movi_i32(mxu_gpr[XRa - 1], 0);
2442 } else if (unlikely(XRb == XRc)) {
2443 /* both operands same registers -> just set destination to zero */
2444 - tcg_gen_movi_tl(mxu_gpr[XRa - 1], 0);
2444 + tcg_gen_movi_i32(mxu_gpr[XRa - 1], 0);
2445 } else {
2446 /* the most general case */
2447 - TCGv t0 = tcg_temp_new();
2448 - TCGv t1 = tcg_temp_new();
2447 + TCGv_i32 t0 = tcg_temp_new_i32();
2448 + TCGv_i32 t1 = tcg_temp_new_i32();
2449
2450 gen_load_mxu_gpr(t0, XRb);
2451 gen_load_mxu_gpr(t1, XRc);
2452 - tcg_gen_setcond_tl(TCG_COND_LT, mxu_gpr[XRa - 1], t0, t1);
2452 + tcg_gen_setcond_i32(TCG_COND_LT, mxu_gpr[XRa - 1], t0, t1);
2453 }
2454 }
2455
@@ -2474,28 +2474,28 @@ static void gen_mxu_D16SLT(DisasContext *ctx)
2474 /* destination is zero register -> do nothing */
2475 } else if (unlikely((XRb == 0) && (XRc == 0))) {
2476 /* both operands zero registers -> just set destination to zero */
2477 - tcg_gen_movi_tl(mxu_gpr[XRa - 1], 0);
2477 + tcg_gen_movi_i32(mxu_gpr[XRa - 1], 0);
2478 } else if (unlikely(XRb == XRc)) {
2479 /* both operands same registers -> just set destination to zero */
2480 - tcg_gen_movi_tl(mxu_gpr[XRa - 1], 0);
2480 + tcg_gen_movi_i32(mxu_gpr[XRa - 1], 0);
2481 } else {
2482 /* the most general case */
2483 - TCGv t0 = tcg_temp_new();
2484 - TCGv t1 = tcg_temp_new();
2485 - TCGv t2 = tcg_temp_new();
2486 - TCGv t3 = tcg_temp_new();
2487 - TCGv t4 = tcg_temp_new();
2483 + TCGv_i32 t0 = tcg_temp_new_i32();
2484 + TCGv_i32 t1 = tcg_temp_new_i32();
2485 + TCGv_i32 t2 = tcg_temp_new_i32();
2486 + TCGv_i32 t3 = tcg_temp_new_i32();
2487 + TCGv_i32 t4 = tcg_temp_new_i32();
2488
2489 gen_load_mxu_gpr(t3, XRb);
2490 gen_load_mxu_gpr(t4, XRc);
2491 - tcg_gen_sextract_tl(t0, t3, 16, 16);
2492 - tcg_gen_sextract_tl(t1, t4, 16, 16);
2493 - tcg_gen_setcond_tl(TCG_COND_LT, t0, t0, t1);
2494 - tcg_gen_shli_tl(t2, t0, 16);
2495 - tcg_gen_sextract_tl(t0, t3, 0, 16);
2496 - tcg_gen_sextract_tl(t1, t4, 0, 16);
2497 - tcg_gen_setcond_tl(TCG_COND_LT, t0, t0, t1);
2498 - tcg_gen_or_tl(mxu_gpr[XRa - 1], t2, t0);
2491 + tcg_gen_sextract_i32(t0, t3, 16, 16);
2492 + tcg_gen_sextract_i32(t1, t4, 16, 16);
2493 + tcg_gen_setcond_i32(TCG_COND_LT, t0, t0, t1);
2494 + tcg_gen_shli_i32(t2, t0, 16);
2495 + tcg_gen_sextract_i32(t0, t3, 0, 16);
2496 + tcg_gen_sextract_i32(t1, t4, 0, 16);
2497 + tcg_gen_setcond_i32(TCG_COND_LT, t0, t0, t1);
2498 + tcg_gen_or_i32(mxu_gpr[XRa - 1], t2, t0);
2499 }
2500 }
2501
@@ -2525,36 +2525,36 @@ static void gen_mxu_d16avg(DisasContext *ctx, bool round45)
2525 /* destination is zero register -> do nothing */
2526 } else if (unlikely((XRb == 0) && (XRc == 0))) {
2527 /* both operands zero registers -> just set destination to zero */
2528 - tcg_gen_movi_tl(mxu_gpr[XRa - 1], 0);
2528 + tcg_gen_movi_i32(mxu_gpr[XRa - 1], 0);
2529 } else if (unlikely(XRb == XRc)) {
2530 /* both operands same registers -> just set destination to same */
2531 - tcg_gen_mov_tl(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1]);
2531 + tcg_gen_mov_i32(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1]);
2532 } else {
2533 /* the most general case */
2534 - TCGv t0 = tcg_temp_new();
2535 - TCGv t1 = tcg_temp_new();
2536 - TCGv t2 = tcg_temp_new();
2537 - TCGv t3 = tcg_temp_new();
2538 - TCGv t4 = tcg_temp_new();
2534 + TCGv_i32 t0 = tcg_temp_new_i32();
2535 + TCGv_i32 t1 = tcg_temp_new_i32();
2536 + TCGv_i32 t2 = tcg_temp_new_i32();
2537 + TCGv_i32 t3 = tcg_temp_new_i32();
2538 + TCGv_i32 t4 = tcg_temp_new_i32();
2539
2540 gen_load_mxu_gpr(t3, XRb);
2541 gen_load_mxu_gpr(t4, XRc);
2542 - tcg_gen_sextract_tl(t0, t3, 16, 16);
2543 - tcg_gen_sextract_tl(t1, t4, 16, 16);
2544 - tcg_gen_add_tl(t0, t0, t1);
2542 + tcg_gen_sextract_i32(t0, t3, 16, 16);
2543 + tcg_gen_sextract_i32(t1, t4, 16, 16);
2544 + tcg_gen_add_i32(t0, t0, t1);
2545 if (round45) {
2546 - tcg_gen_addi_tl(t0, t0, 1);
2546 + tcg_gen_addi_i32(t0, t0, 1);
2547 }
2548 - tcg_gen_shli_tl(t2, t0, 15);
2549 - tcg_gen_andi_tl(t2, t2, 0xffff0000);
2550 - tcg_gen_sextract_tl(t0, t3, 0, 16);
2551 - tcg_gen_sextract_tl(t1, t4, 0, 16);
2552 - tcg_gen_add_tl(t0, t0, t1);
2548 + tcg_gen_shli_i32(t2, t0, 15);
2549 + tcg_gen_andi_i32(t2, t2, 0xffff0000);
2550 + tcg_gen_sextract_i32(t0, t3, 0, 16);
2551 + tcg_gen_sextract_i32(t1, t4, 0, 16);
2552 + tcg_gen_add_i32(t0, t0, t1);
2553 if (round45) {
2554 - tcg_gen_addi_tl(t0, t0, 1);
2554 + tcg_gen_addi_i32(t0, t0, 1);
2555 }
2556 - tcg_gen_shri_tl(t0, t0, 1);
2557 - tcg_gen_deposit_tl(t2, t2, t0, 0, 16);
2556 + tcg_gen_shri_i32(t0, t0, 1);
2557 + tcg_gen_deposit_i32(t2, t2, t0, 0, 16);
2558 gen_store_mxu_gpr(t2, XRa);
2559 }
2560 }
@@ -2585,31 +2585,31 @@ static void gen_mxu_q8avg(DisasContext *ctx, bool round45)
2585 /* destination is zero register -> do nothing */
2586 } else if (unlikely((XRb == 0) && (XRc == 0))) {
2587 /* both operands zero registers -> just set destination to zero */
2588 - tcg_gen_movi_tl(mxu_gpr[XRa - 1], 0);
2588 + tcg_gen_movi_i32(mxu_gpr[XRa - 1], 0);
2589 } else if (unlikely(XRb == XRc)) {
2590 /* both operands same registers -> just set destination to same */
2591 - tcg_gen_mov_tl(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1]);
2591 + tcg_gen_mov_i32(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1]);
2592 } else {
2593 /* the most general case */
2594 - TCGv t0 = tcg_temp_new();
2595 - TCGv t1 = tcg_temp_new();
2596 - TCGv t2 = tcg_temp_new();
2597 - TCGv t3 = tcg_temp_new();
2598 - TCGv t4 = tcg_temp_new();
2594 + TCGv_i32 t0 = tcg_temp_new_i32();
2595 + TCGv_i32 t1 = tcg_temp_new_i32();
2596 + TCGv_i32 t2 = tcg_temp_new_i32();
2597 + TCGv_i32 t3 = tcg_temp_new_i32();
2598 + TCGv_i32 t4 = tcg_temp_new_i32();
2599
2600 gen_load_mxu_gpr(t3, XRb);
2601 gen_load_mxu_gpr(t4, XRc);
2602 - tcg_gen_movi_tl(t2, 0);
2602 + tcg_gen_movi_i32(t2, 0);
2603
2604 for (int i = 0; i < 4; i++) {
2605 - tcg_gen_extract_tl(t0, t3, 8 * i, 8);
2606 - tcg_gen_extract_tl(t1, t4, 8 * i, 8);
2607 - tcg_gen_add_tl(t0, t0, t1);
2605 + tcg_gen_extract_i32(t0, t3, 8 * i, 8);
2606 + tcg_gen_extract_i32(t1, t4, 8 * i, 8);
2607 + tcg_gen_add_i32(t0, t0, t1);
2608 if (round45) {
2609 - tcg_gen_addi_tl(t0, t0, 1);
2609 + tcg_gen_addi_i32(t0, t0, 1);
2610 }
2611 - tcg_gen_shri_tl(t0, t0, 1);
2612 - tcg_gen_deposit_tl(t2, t2, t0, 8 * i, 8);
2611 + tcg_gen_shri_i32(t0, t0, 1);
2612 + tcg_gen_deposit_i32(t2, t2, t0, 8 * i, 8);
2613 }
2614 gen_store_mxu_gpr(t2, XRa);
2615 }
@@ -2636,10 +2636,10 @@ static void gen_mxu_q8movzn(DisasContext *ctx, TCGCond cond)
2636 XRb = extract32(ctx->opcode, 10, 4);
2637 XRc = extract32(ctx->opcode, 14, 4);
2638
2639 - TCGv t0 = tcg_temp_new();
2640 - TCGv t1 = tcg_temp_new();
2641 - TCGv t2 = tcg_temp_new();
2642 - TCGv t3 = tcg_temp_new();
2639 + TCGv_i32 t0 = tcg_temp_new_i32();
2640 + TCGv_i32 t1 = tcg_temp_new_i32();
2641 + TCGv_i32 t2 = tcg_temp_new_i32();
2642 + TCGv_i32 t3 = tcg_temp_new_i32();
2643 TCGLabel *l_quarterdone = gen_new_label();
2644 TCGLabel *l_halfdone = gen_new_label();
2645 TCGLabel *l_quarterrest = gen_new_label();
@@ -2649,28 +2649,28 @@ static void gen_mxu_q8movzn(DisasContext *ctx, TCGCond cond)
2649 gen_load_mxu_gpr(t1, XRb);
2650 gen_load_mxu_gpr(t2, XRa);
2651
2652 - tcg_gen_extract_tl(t3, t1, 24, 8);
2653 - tcg_gen_brcondi_tl(cond, t3, 0, l_quarterdone);
2654 - tcg_gen_extract_tl(t3, t0, 24, 8);
2655 - tcg_gen_deposit_tl(t2, t2, t3, 24, 8);
2652 + tcg_gen_extract_i32(t3, t1, 24, 8);
2653 + tcg_gen_brcondi_i32(cond, t3, 0, l_quarterdone);
2654 + tcg_gen_extract_i32(t3, t0, 24, 8);
2655 + tcg_gen_deposit_i32(t2, t2, t3, 24, 8);
2656
2657 gen_set_label(l_quarterdone);
2658 - tcg_gen_extract_tl(t3, t1, 16, 8);
2659 - tcg_gen_brcondi_tl(cond, t3, 0, l_halfdone);
2660 - tcg_gen_extract_tl(t3, t0, 16, 8);
2661 - tcg_gen_deposit_tl(t2, t2, t3, 16, 8);
2658 + tcg_gen_extract_i32(t3, t1, 16, 8);
2659 + tcg_gen_brcondi_i32(cond, t3, 0, l_halfdone);
2660 + tcg_gen_extract_i32(t3, t0, 16, 8);
2661 + tcg_gen_deposit_i32(t2, t2, t3, 16, 8);
2662
2663 gen_set_label(l_halfdone);
2664 - tcg_gen_extract_tl(t3, t1, 8, 8);
2665 - tcg_gen_brcondi_tl(cond, t3, 0, l_quarterrest);
2666 - tcg_gen_extract_tl(t3, t0, 8, 8);
2667 - tcg_gen_deposit_tl(t2, t2, t3, 8, 8);
2664 + tcg_gen_extract_i32(t3, t1, 8, 8);
2665 + tcg_gen_brcondi_i32(cond, t3, 0, l_quarterrest);
2666 + tcg_gen_extract_i32(t3, t0, 8, 8);
2667 + tcg_gen_deposit_i32(t2, t2, t3, 8, 8);
2668
2669 gen_set_label(l_quarterrest);
2670 - tcg_gen_extract_tl(t3, t1, 0, 8);
2671 - tcg_gen_brcondi_tl(cond, t3, 0, l_done);
2672 - tcg_gen_extract_tl(t3, t0, 0, 8);
2673 - tcg_gen_deposit_tl(t2, t2, t3, 0, 8);
2670 + tcg_gen_extract_i32(t3, t1, 0, 8);
2671 + tcg_gen_brcondi_i32(cond, t3, 0, l_done);
2672 + tcg_gen_extract_i32(t3, t0, 0, 8);
2673 + tcg_gen_deposit_i32(t2, t2, t3, 0, 8);
2674
2675 gen_set_label(l_done);
2676 gen_store_mxu_gpr(t2, XRa);
@@ -2697,10 +2697,10 @@ static void gen_mxu_d16movzn(DisasContext *ctx, TCGCond cond)
2697 XRb = extract32(ctx->opcode, 10, 4);
2698 XRc = extract32(ctx->opcode, 14, 4);
2699
2700 - TCGv t0 = tcg_temp_new();
2701 - TCGv t1 = tcg_temp_new();
2702 - TCGv t2 = tcg_temp_new();
2703 - TCGv t3 = tcg_temp_new();
2700 + TCGv_i32 t0 = tcg_temp_new_i32();
2701 + TCGv_i32 t1 = tcg_temp_new_i32();
2702 + TCGv_i32 t2 = tcg_temp_new_i32();
2703 + TCGv_i32 t3 = tcg_temp_new_i32();
2704 TCGLabel *l_halfdone = gen_new_label();
2705 TCGLabel *l_done = gen_new_label();
2706
@@ -2708,16 +2708,16 @@ static void gen_mxu_d16movzn(DisasContext *ctx, TCGCond cond)
2708 gen_load_mxu_gpr(t1, XRb);
2709 gen_load_mxu_gpr(t2, XRa);
2710
2711 - tcg_gen_extract_tl(t3, t1, 16, 16);
2712 - tcg_gen_brcondi_tl(cond, t3, 0, l_halfdone);
2713 - tcg_gen_extract_tl(t3, t0, 16, 16);
2714 - tcg_gen_deposit_tl(t2, t2, t3, 16, 16);
2711 + tcg_gen_extract_i32(t3, t1, 16, 16);
2712 + tcg_gen_brcondi_i32(cond, t3, 0, l_halfdone);
2713 + tcg_gen_extract_i32(t3, t0, 16, 16);
2714 + tcg_gen_deposit_i32(t2, t2, t3, 16, 16);
2715
2716 gen_set_label(l_halfdone);
2717 - tcg_gen_extract_tl(t3, t1, 0, 16);
2718 - tcg_gen_brcondi_tl(cond, t3, 0, l_done);
2719 - tcg_gen_extract_tl(t3, t0, 0, 16);
2720 - tcg_gen_deposit_tl(t2, t2, t3, 0, 16);
2717 + tcg_gen_extract_i32(t3, t1, 0, 16);
2718 + tcg_gen_brcondi_i32(cond, t3, 0, l_done);
2719 + tcg_gen_extract_i32(t3, t0, 0, 16);
2720 + tcg_gen_deposit_i32(t2, t2, t3, 0, 16);
2721
2722 gen_set_label(l_done);
2723 gen_store_mxu_gpr(t2, XRa);
@@ -2744,14 +2744,14 @@ static void gen_mxu_s32movzn(DisasContext *ctx, TCGCond cond)
2744 XRb = extract32(ctx->opcode, 10, 4);
2745 XRc = extract32(ctx->opcode, 14, 4);
2746
2747 - TCGv t0 = tcg_temp_new();
2748 - TCGv t1 = tcg_temp_new();
2747 + TCGv_i32 t0 = tcg_temp_new_i32();
2748 + TCGv_i32 t1 = tcg_temp_new_i32();
2749 TCGLabel *l_done = gen_new_label();
2750
2751 gen_load_mxu_gpr(t0, XRc);
2752 gen_load_mxu_gpr(t1, XRb);
2753
2754 - tcg_gen_brcondi_tl(cond, t1, 0, l_done);
2754 + tcg_gen_brcondi_i32(cond, t1, 0, l_done);
2755 gen_store_mxu_gpr(t0, XRa);
2756 gen_set_label(l_done);
2757 }
@@ -2784,18 +2784,18 @@ static void gen_mxu_S32CPS(DisasContext *ctx)
2784 /* destination is zero register -> do nothing */
2785 } else if (unlikely(XRb == 0)) {
2786 /* XRc make no sense 0 - 0 = 0 -> just set destination to zero */
2787 - tcg_gen_movi_tl(mxu_gpr[XRa - 1], 0);
2787 + tcg_gen_movi_i32(mxu_gpr[XRa - 1], 0);
2788 } else if (unlikely(XRc == 0)) {
2789 /* condition always false -> just move XRb to XRa */
2790 - tcg_gen_mov_tl(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1]);
2790 + tcg_gen_mov_i32(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1]);
2791 } else {
2792 /* the most general case */
2793 - TCGv t0 = tcg_temp_new();
2793 + TCGv_i32 t0 = tcg_temp_new_i32();
2794 TCGLabel *l_not_less = gen_new_label();
2795 TCGLabel *l_done = gen_new_label();
2796
2797 - tcg_gen_brcondi_tl(TCG_COND_GE, mxu_gpr[XRc - 1], 0, l_not_less);
2798 - tcg_gen_neg_tl(t0, mxu_gpr[XRb - 1]);
2797 + tcg_gen_brcondi_i32(TCG_COND_GE, mxu_gpr[XRc - 1], 0, l_not_less);
2798 + tcg_gen_neg_i32(t0, mxu_gpr[XRb - 1]);
2799 tcg_gen_br(l_done);
2800 gen_set_label(l_not_less);
2801 gen_load_mxu_gpr(t0, XRb);
@@ -2824,37 +2824,37 @@ static void gen_mxu_D16CPS(DisasContext *ctx)
2824 /* destination is zero register -> do nothing */
2825 } else if (unlikely(XRb == 0)) {
2826 /* XRc make no sense 0 - 0 = 0 -> just set destination to zero */
2827 - tcg_gen_movi_tl(mxu_gpr[XRa - 1], 0);
2827 + tcg_gen_movi_i32(mxu_gpr[XRa - 1], 0);
2828 } else if (unlikely(XRc == 0)) {
2829 /* condition always false -> just move XRb to XRa */
2830 - tcg_gen_mov_tl(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1]);
2830 + tcg_gen_mov_i32(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1]);
2831 } else {
2832 /* the most general case */
2833 - TCGv t0 = tcg_temp_new();
2834 - TCGv t1 = tcg_temp_new();
2833 + TCGv_i32 t0 = tcg_temp_new_i32();
2834 + TCGv_i32 t1 = tcg_temp_new_i32();
2835 TCGLabel *l_done_hi = gen_new_label();
2836 TCGLabel *l_not_less_lo = gen_new_label();
2837 TCGLabel *l_done_lo = gen_new_label();
2838
2839 - tcg_gen_sextract_tl(t0, mxu_gpr[XRc - 1], 16, 16);
2840 - tcg_gen_sextract_tl(t1, mxu_gpr[XRb - 1], 16, 16);
2841 - tcg_gen_brcondi_tl(TCG_COND_GE, t0, 0, l_done_hi);
2842 - tcg_gen_subfi_tl(t1, 0, t1);
2839 + tcg_gen_sextract_i32(t0, mxu_gpr[XRc - 1], 16, 16);
2840 + tcg_gen_sextract_i32(t1, mxu_gpr[XRb - 1], 16, 16);
2841 + tcg_gen_brcondi_i32(TCG_COND_GE, t0, 0, l_done_hi);
2842 + tcg_gen_subfi_i32(t1, 0, t1);
2843
2844 gen_set_label(l_done_hi);
2845 tcg_gen_shli_i32(t1, t1, 16);
2846
2847 - tcg_gen_sextract_tl(t0, mxu_gpr[XRc - 1], 0, 16);
2848 - tcg_gen_brcondi_tl(TCG_COND_GE, t0, 0, l_not_less_lo);
2849 - tcg_gen_sextract_tl(t0, mxu_gpr[XRb - 1], 0, 16);
2850 - tcg_gen_subfi_tl(t0, 0, t0);
2847 + tcg_gen_sextract_i32(t0, mxu_gpr[XRc - 1], 0, 16);
2848 + tcg_gen_brcondi_i32(TCG_COND_GE, t0, 0, l_not_less_lo);
2849 + tcg_gen_sextract_i32(t0, mxu_gpr[XRb - 1], 0, 16);
2850 + tcg_gen_subfi_i32(t0, 0, t0);
2851 tcg_gen_br(l_done_lo);
2852
2853 gen_set_label(l_not_less_lo);
2854 - tcg_gen_extract_tl(t0, mxu_gpr[XRb - 1], 0, 16);
2854 + tcg_gen_extract_i32(t0, mxu_gpr[XRb - 1], 0, 16);
2855
2856 gen_set_label(l_done_lo);
2857 - tcg_gen_deposit_tl(mxu_gpr[XRa - 1], t1, t0, 0, 16);
2857 + tcg_gen_deposit_i32(mxu_gpr[XRa - 1], t1, t0, 0, 16);
2858 }
2859 }
2860
@@ -2880,27 +2880,27 @@ static void gen_mxu_Q8ABD(DisasContext *ctx)
2880 /* destination is zero register -> do nothing */
2881 } else if (unlikely((XRb == 0) && (XRc == 0))) {
2882 /* both operands zero registers -> just set destination to zero */
2883 - tcg_gen_movi_tl(mxu_gpr[XRa - 1], 0);
2883 + tcg_gen_movi_i32(mxu_gpr[XRa - 1], 0);
2884 } else {
2885 /* the most general case */
2886 - TCGv t0 = tcg_temp_new();
2887 - TCGv t1 = tcg_temp_new();
2888 - TCGv t2 = tcg_temp_new();
2889 - TCGv t3 = tcg_temp_new();
2890 - TCGv t4 = tcg_temp_new();
2886 + TCGv_i32 t0 = tcg_temp_new_i32();
2887 + TCGv_i32 t1 = tcg_temp_new_i32();
2888 + TCGv_i32 t2 = tcg_temp_new_i32();
2889 + TCGv_i32 t3 = tcg_temp_new_i32();
2890 + TCGv_i32 t4 = tcg_temp_new_i32();
2891
2892 gen_load_mxu_gpr(t3, XRb);
2893 gen_load_mxu_gpr(t4, XRc);
2894 - tcg_gen_movi_tl(t2, 0);
2894 + tcg_gen_movi_i32(t2, 0);
2895
2896 for (int i = 0; i < 4; i++) {
2897 - tcg_gen_extract_tl(t0, t3, 8 * i, 8);
2898 - tcg_gen_extract_tl(t1, t4, 8 * i, 8);
2897 + tcg_gen_extract_i32(t0, t3, 8 * i, 8);
2898 + tcg_gen_extract_i32(t1, t4, 8 * i, 8);
2899
2900 - tcg_gen_sub_tl(t0, t0, t1);
2901 - tcg_gen_abs_tl(t0, t0);
2900 + tcg_gen_sub_i32(t0, t0, t1);
2901 + tcg_gen_abs_i32(t0, t0);
2902
2903 - tcg_gen_deposit_tl(t2, t2, t0, 8 * i, 8);
2903 + tcg_gen_deposit_i32(t2, t2, t0, 8 * i, 8);
2904 }
2905 gen_store_mxu_gpr(t2, XRa);
2906 }
@@ -2930,41 +2930,41 @@ static void gen_mxu_Q8ADD(DisasContext *ctx)
2930 tcg_gen_movi_i32(mxu_gpr[XRa - 1], 0);
2931 } else {
2932 /* the most general case */
2933 - TCGv t0 = tcg_temp_new();
2934 - TCGv t1 = tcg_temp_new();
2935 - TCGv t2 = tcg_temp_new();
2936 - TCGv t3 = tcg_temp_new();
2937 - TCGv t4 = tcg_temp_new();
2933 + TCGv_i32 t0 = tcg_temp_new_i32();
2934 + TCGv_i32 t1 = tcg_temp_new_i32();
2935 + TCGv_i32 t2 = tcg_temp_new_i32();
2936 + TCGv_i32 t3 = tcg_temp_new_i32();
2937 + TCGv_i32 t4 = tcg_temp_new_i32();
2938
2939 gen_load_mxu_gpr(t3, XRb);
2940 gen_load_mxu_gpr(t4, XRc);
2941
2942 for (int i = 0; i < 4; i++) {
2943 - tcg_gen_andi_tl(t0, t3, 0xff);
2944 - tcg_gen_andi_tl(t1, t4, 0xff);
2943 + tcg_gen_andi_i32(t0, t3, 0xff);
2944 + tcg_gen_andi_i32(t1, t4, 0xff);
2945
2946 if (i < 2) {
2947 if (aptn2 & 0x01) {
2948 - tcg_gen_sub_tl(t0, t0, t1);
2948 + tcg_gen_sub_i32(t0, t0, t1);
2949 } else {
2950 - tcg_gen_add_tl(t0, t0, t1);
2950 + tcg_gen_add_i32(t0, t0, t1);
2951 }
2952 } else {
2953 if (aptn2 & 0x02) {
2954 - tcg_gen_sub_tl(t0, t0, t1);
2954 + tcg_gen_sub_i32(t0, t0, t1);
2955 } else {
2956 - tcg_gen_add_tl(t0, t0, t1);
2956 + tcg_gen_add_i32(t0, t0, t1);
2957 }
2958 }
2959 if (i < 3) {
2960 - tcg_gen_shri_tl(t3, t3, 8);
2961 - tcg_gen_shri_tl(t4, t4, 8);
2960 + tcg_gen_shri_i32(t3, t3, 8);
2961 + tcg_gen_shri_i32(t4, t4, 8);
2962 }
2963 if (i > 0) {
2964 - tcg_gen_deposit_tl(t2, t2, t0, 8 * i, 8);
2964 + tcg_gen_deposit_i32(t2, t2, t0, 8 * i, 8);
2965 } else {
2966 - tcg_gen_andi_tl(t0, t0, 0xff);
2967 - tcg_gen_mov_tl(t2, t0);
2966 + tcg_gen_andi_i32(t0, t0, 0xff);
2967 + tcg_gen_mov_i32(t2, t0);
2968 }
2969 }
2970 gen_store_mxu_gpr(t2, XRa);
@@ -2999,19 +2999,19 @@ static void gen_mxu_q8adde(DisasContext *ctx, bool accumulate)
2999 if (unlikely((XRb == 0) && (XRc == 0))) {
3000 /* both operands zero registers -> just set destination to zero */
3001 if (XRa != 0) {
3002 - tcg_gen_movi_tl(mxu_gpr[XRa - 1], 0);
3002 + tcg_gen_movi_i32(mxu_gpr[XRa - 1], 0);
3003 }
3004 if (XRd != 0) {
3005 - tcg_gen_movi_tl(mxu_gpr[XRd - 1], 0);
3005 + tcg_gen_movi_i32(mxu_gpr[XRd - 1], 0);
3006 }
3007 } else {
3008 /* the most general case */
3009 - TCGv t0 = tcg_temp_new();
3010 - TCGv t1 = tcg_temp_new();
3011 - TCGv t2 = tcg_temp_new();
3012 - TCGv t3 = tcg_temp_new();
3013 - TCGv t4 = tcg_temp_new();
3014 - TCGv t5 = tcg_temp_new();
3009 + TCGv_i32 t0 = tcg_temp_new_i32();
3010 + TCGv_i32 t1 = tcg_temp_new_i32();
3011 + TCGv_i32 t2 = tcg_temp_new_i32();
3012 + TCGv_i32 t3 = tcg_temp_new_i32();
3013 + TCGv_i32 t4 = tcg_temp_new_i32();
3014 + TCGv_i32 t5 = tcg_temp_new_i32();
3015
3016 if (XRa != 0) {
3017 gen_extract_mxu_gpr(t0, XRb, 16, 8);
@@ -3019,22 +3019,22 @@ static void gen_mxu_q8adde(DisasContext *ctx, bool accumulate)
3019 gen_extract_mxu_gpr(t2, XRb, 24, 8);
3020 gen_extract_mxu_gpr(t3, XRc, 24, 8);
3021 if (aptn2 & 2) {
3022 - tcg_gen_sub_tl(t0, t0, t1);
3023 - tcg_gen_sub_tl(t2, t2, t3);
3022 + tcg_gen_sub_i32(t0, t0, t1);
3023 + tcg_gen_sub_i32(t2, t2, t3);
3024 } else {
3025 - tcg_gen_add_tl(t0, t0, t1);
3026 - tcg_gen_add_tl(t2, t2, t3);
3025 + tcg_gen_add_i32(t0, t0, t1);
3026 + tcg_gen_add_i32(t2, t2, t3);
3027 }
3028 if (accumulate) {
3029 gen_load_mxu_gpr(t5, XRa);
3030 - tcg_gen_extract_tl(t1, t5, 0, 16);
3031 - tcg_gen_extract_tl(t3, t5, 16, 16);
3032 - tcg_gen_add_tl(t0, t0, t1);
3033 - tcg_gen_add_tl(t2, t2, t3);
3030 + tcg_gen_extract_i32(t1, t5, 0, 16);
3031 + tcg_gen_extract_i32(t3, t5, 16, 16);
3032 + tcg_gen_add_i32(t0, t0, t1);
3033 + tcg_gen_add_i32(t2, t2, t3);
3034 }
3035 - tcg_gen_shli_tl(t2, t2, 16);
3036 - tcg_gen_extract_tl(t0, t0, 0, 16);
3037 - tcg_gen_or_tl(t4, t2, t0);
3035 + tcg_gen_shli_i32(t2, t2, 16);
3036 + tcg_gen_extract_i32(t0, t0, 0, 16);
3037 + tcg_gen_or_i32(t4, t2, t0);
3038 }
3039 if (XRd != 0) {
3040 gen_extract_mxu_gpr(t0, XRb, 0, 8);
@@ -3042,22 +3042,22 @@ static void gen_mxu_q8adde(DisasContext *ctx, bool accumulate)
3042 gen_extract_mxu_gpr(t2, XRb, 8, 8);
3043 gen_extract_mxu_gpr(t3, XRc, 8, 8);
3044 if (aptn2 & 1) {
3045 - tcg_gen_sub_tl(t0, t0, t1);
3046 - tcg_gen_sub_tl(t2, t2, t3);
3045 + tcg_gen_sub_i32(t0, t0, t1);
3046 + tcg_gen_sub_i32(t2, t2, t3);
3047 } else {
3048 - tcg_gen_add_tl(t0, t0, t1);
3049 - tcg_gen_add_tl(t2, t2, t3);
3048 + tcg_gen_add_i32(t0, t0, t1);
3049 + tcg_gen_add_i32(t2, t2, t3);
3050 }
3051 if (accumulate) {
3052 gen_load_mxu_gpr(t5, XRd);
3053 - tcg_gen_extract_tl(t1, t5, 0, 16);
3054 - tcg_gen_extract_tl(t3, t5, 16, 16);
3055 - tcg_gen_add_tl(t0, t0, t1);
3056 - tcg_gen_add_tl(t2, t2, t3);
3053 + tcg_gen_extract_i32(t1, t5, 0, 16);
3054 + tcg_gen_extract_i32(t3, t5, 16, 16);
3055 + tcg_gen_add_i32(t0, t0, t1);
3056 + tcg_gen_add_i32(t2, t2, t3);
3057 }
3058 - tcg_gen_shli_tl(t2, t2, 16);
3059 - tcg_gen_extract_tl(t0, t0, 0, 16);
3060 - tcg_gen_or_tl(t5, t2, t0);
3058 + tcg_gen_shli_i32(t2, t2, 16);
3059 + tcg_gen_extract_i32(t0, t0, 0, 16);
3060 + tcg_gen_or_i32(t5, t2, t0);
3061 }
3062
3063 gen_store_mxu_gpr(t4, XRa);
@@ -3090,46 +3090,46 @@ static void gen_mxu_d8sum(DisasContext *ctx, bool sumc)
3090 /* destination is zero register -> do nothing */
3091 } else if (unlikely((XRb == 0) && (XRc == 0))) {
3092 /* both operands zero registers -> just set destination to zero */
3093 - tcg_gen_movi_tl(mxu_gpr[XRa - 1], 0);
3093 + tcg_gen_movi_i32(mxu_gpr[XRa - 1], 0);
3094 } else {
3095 /* the most general case */
3096 - TCGv t0 = tcg_temp_new();
3097 - TCGv t1 = tcg_temp_new();
3098 - TCGv t2 = tcg_temp_new();
3099 - TCGv t3 = tcg_temp_new();
3100 - TCGv t4 = tcg_temp_new();
3101 - TCGv t5 = tcg_temp_new();
3096 + TCGv_i32 t0 = tcg_temp_new_i32();
3097 + TCGv_i32 t1 = tcg_temp_new_i32();
3098 + TCGv_i32 t2 = tcg_temp_new_i32();
3099 + TCGv_i32 t3 = tcg_temp_new_i32();
3100 + TCGv_i32 t4 = tcg_temp_new_i32();
3101 + TCGv_i32 t5 = tcg_temp_new_i32();
3102
3103 if (XRb != 0) {
3104 - tcg_gen_extract_tl(t0, mxu_gpr[XRb - 1], 0, 8);
3105 - tcg_gen_extract_tl(t1, mxu_gpr[XRb - 1], 8, 8);
3106 - tcg_gen_extract_tl(t2, mxu_gpr[XRb - 1], 16, 8);
3107 - tcg_gen_extract_tl(t3, mxu_gpr[XRb - 1], 24, 8);
3108 - tcg_gen_add_tl(t4, t0, t1);
3109 - tcg_gen_add_tl(t4, t4, t2);
3110 - tcg_gen_add_tl(t4, t4, t3);
3104 + tcg_gen_extract_i32(t0, mxu_gpr[XRb - 1], 0, 8);
3105 + tcg_gen_extract_i32(t1, mxu_gpr[XRb - 1], 8, 8);
3106 + tcg_gen_extract_i32(t2, mxu_gpr[XRb - 1], 16, 8);
3107 + tcg_gen_extract_i32(t3, mxu_gpr[XRb - 1], 24, 8);
3108 + tcg_gen_add_i32(t4, t0, t1);
3109 + tcg_gen_add_i32(t4, t4, t2);
3110 + tcg_gen_add_i32(t4, t4, t3);
3111 } else {
3112 - tcg_gen_mov_tl(t4, 0);
3112 + tcg_gen_mov_i32(t4, 0);
3113 }
3114 if (XRc != 0) {
3115 - tcg_gen_extract_tl(t0, mxu_gpr[XRc - 1], 0, 8);
3116 - tcg_gen_extract_tl(t1, mxu_gpr[XRc - 1], 8, 8);
3117 - tcg_gen_extract_tl(t2, mxu_gpr[XRc - 1], 16, 8);
3118 - tcg_gen_extract_tl(t3, mxu_gpr[XRc - 1], 24, 8);
3119 - tcg_gen_add_tl(t5, t0, t1);
3120 - tcg_gen_add_tl(t5, t5, t2);
3121 - tcg_gen_add_tl(t5, t5, t3);
3115 + tcg_gen_extract_i32(t0, mxu_gpr[XRc - 1], 0, 8);
3116 + tcg_gen_extract_i32(t1, mxu_gpr[XRc - 1], 8, 8);
3117 + tcg_gen_extract_i32(t2, mxu_gpr[XRc - 1], 16, 8);
3118 + tcg_gen_extract_i32(t3, mxu_gpr[XRc - 1], 24, 8);
3119 + tcg_gen_add_i32(t5, t0, t1);
3120 + tcg_gen_add_i32(t5, t5, t2);
3121 + tcg_gen_add_i32(t5, t5, t3);
3122 } else {
3123 - tcg_gen_mov_tl(t5, 0);
3123 + tcg_gen_mov_i32(t5, 0);
3124 }
3125
3126 if (sumc) {
3127 - tcg_gen_addi_tl(t4, t4, 2);
3128 - tcg_gen_addi_tl(t5, t5, 2);
3127 + tcg_gen_addi_i32(t4, t4, 2);
3128 + tcg_gen_addi_i32(t5, t5, 2);
3129 }
3130 - tcg_gen_shli_tl(t4, t4, 16);
3130 + tcg_gen_shli_i32(t4, t4, 16);
3131
3132 - tcg_gen_or_tl(mxu_gpr[XRa - 1], t4, t5);
3132 + tcg_gen_or_i32(mxu_gpr[XRa - 1], t4, t5);
3133 }
3134 }
3135
@@ -3148,74 +3148,74 @@ static void gen_mxu_q16add(DisasContext *ctx)
3148 XRb = extract32(ctx->opcode, 10, 4);
3149 XRa = extract32(ctx->opcode, 6, 4);
3150
3151 - TCGv t0 = tcg_temp_new();
3152 - TCGv t1 = tcg_temp_new();
3153 - TCGv t2 = tcg_temp_new();
3154 - TCGv t3 = tcg_temp_new();
3155 - TCGv t4 = tcg_temp_new();
3156 - TCGv t5 = tcg_temp_new();
3151 + TCGv_i32 t0 = tcg_temp_new_i32();
3152 + TCGv_i32 t1 = tcg_temp_new_i32();
3153 + TCGv_i32 t2 = tcg_temp_new_i32();
3154 + TCGv_i32 t3 = tcg_temp_new_i32();
3155 + TCGv_i32 t4 = tcg_temp_new_i32();
3156 + TCGv_i32 t5 = tcg_temp_new_i32();
3157
3158 gen_load_mxu_gpr(t1, XRb);
3159 - tcg_gen_extract_tl(t0, t1, 0, 16);
3160 - tcg_gen_extract_tl(t1, t1, 16, 16);
3159 + tcg_gen_extract_i32(t0, t1, 0, 16);
3160 + tcg_gen_extract_i32(t1, t1, 16, 16);
3161
3162 gen_load_mxu_gpr(t3, XRc);
3163 - tcg_gen_extract_tl(t2, t3, 0, 16);
3164 - tcg_gen_extract_tl(t3, t3, 16, 16);
3163 + tcg_gen_extract_i32(t2, t3, 0, 16);
3164 + tcg_gen_extract_i32(t3, t3, 16, 16);
3165
3166 switch (optn2) {
3167 case MXU_OPTN2_WW: /* XRB.H+XRC.H == lop, XRB.L+XRC.L == rop */
3168 - tcg_gen_mov_tl(t4, t1);
3169 - tcg_gen_mov_tl(t5, t0);
3168 + tcg_gen_mov_i32(t4, t1);
3169 + tcg_gen_mov_i32(t5, t0);
3170 break;
3171 case MXU_OPTN2_LW: /* XRB.L+XRC.H == lop, XRB.L+XRC.L == rop */
3172 - tcg_gen_mov_tl(t4, t0);
3173 - tcg_gen_mov_tl(t5, t0);
3172 + tcg_gen_mov_i32(t4, t0);
3173 + tcg_gen_mov_i32(t5, t0);
3174 break;
3175 case MXU_OPTN2_HW: /* XRB.H+XRC.H == lop, XRB.H+XRC.L == rop */
3176 - tcg_gen_mov_tl(t4, t1);
3177 - tcg_gen_mov_tl(t5, t1);
3176 + tcg_gen_mov_i32(t4, t1);
3177 + tcg_gen_mov_i32(t5, t1);
3178 break;
3179 case MXU_OPTN2_XW: /* XRB.L+XRC.H == lop, XRB.H+XRC.L == rop */
3180 - tcg_gen_mov_tl(t4, t0);
3181 - tcg_gen_mov_tl(t5, t1);
3180 + tcg_gen_mov_i32(t4, t0);
3181 + tcg_gen_mov_i32(t5, t1);
3182 break;
3183 }
3184
3185 switch (aptn2) {
3186 case MXU_APTN2_AA: /* lop +, rop + */
3187 - tcg_gen_add_tl(t0, t4, t3);
3188 - tcg_gen_add_tl(t1, t5, t2);
3189 - tcg_gen_add_tl(t4, t4, t3);
3190 - tcg_gen_add_tl(t5, t5, t2);
3187 + tcg_gen_add_i32(t0, t4, t3);
3188 + tcg_gen_add_i32(t1, t5, t2);
3189 + tcg_gen_add_i32(t4, t4, t3);
3190 + tcg_gen_add_i32(t5, t5, t2);
3191 break;
3192 case MXU_APTN2_AS: /* lop +, rop + */
3193 - tcg_gen_sub_tl(t0, t4, t3);
3194 - tcg_gen_sub_tl(t1, t5, t2);
3195 - tcg_gen_add_tl(t4, t4, t3);
3196 - tcg_gen_add_tl(t5, t5, t2);
3193 + tcg_gen_sub_i32(t0, t4, t3);
3194 + tcg_gen_sub_i32(t1, t5, t2);
3195 + tcg_gen_add_i32(t4, t4, t3);
3196 + tcg_gen_add_i32(t5, t5, t2);
3197 break;
3198 case MXU_APTN2_SA: /* lop +, rop + */
3199 - tcg_gen_add_tl(t0, t4, t3);
3200 - tcg_gen_add_tl(t1, t5, t2);
3201 - tcg_gen_sub_tl(t4, t4, t3);
3202 - tcg_gen_sub_tl(t5, t5, t2);
3199 + tcg_gen_add_i32(t0, t4, t3);
3200 + tcg_gen_add_i32(t1, t5, t2);
3201 + tcg_gen_sub_i32(t4, t4, t3);
3202 + tcg_gen_sub_i32(t5, t5, t2);
3203 break;
3204 case MXU_APTN2_SS: /* lop +, rop + */
3205 - tcg_gen_sub_tl(t0, t4, t3);
3206 - tcg_gen_sub_tl(t1, t5, t2);
3207 - tcg_gen_sub_tl(t4, t4, t3);
3208 - tcg_gen_sub_tl(t5, t5, t2);
3205 + tcg_gen_sub_i32(t0, t4, t3);
3206 + tcg_gen_sub_i32(t1, t5, t2);
3207 + tcg_gen_sub_i32(t4, t4, t3);
3208 + tcg_gen_sub_i32(t5, t5, t2);
3209 break;
3210 }
3211
3212 - tcg_gen_shli_tl(t0, t0, 16);
3213 - tcg_gen_extract_tl(t1, t1, 0, 16);
3214 - tcg_gen_shli_tl(t4, t4, 16);
3215 - tcg_gen_extract_tl(t5, t5, 0, 16);
3212 + tcg_gen_shli_i32(t0, t0, 16);
3213 + tcg_gen_extract_i32(t1, t1, 0, 16);
3214 + tcg_gen_shli_i32(t4, t4, 16);
3215 + tcg_gen_extract_i32(t5, t5, 0, 16);
3216
3217 - tcg_gen_or_tl(mxu_gpr[XRa - 1], t4, t5);
3218 - tcg_gen_or_tl(mxu_gpr[XRd - 1], t0, t1);
3217 + tcg_gen_or_i32(mxu_gpr[XRa - 1], t4, t5);
3218 + tcg_gen_or_i32(mxu_gpr[XRd - 1], t0, t1);
3219 }
3220
3221 /*
@@ -3232,66 +3232,66 @@ static void gen_mxu_q16acc(DisasContext *ctx)
3232 XRb = extract32(ctx->opcode, 10, 4);
3233 XRa = extract32(ctx->opcode, 6, 4);
3234
3235 - TCGv t0 = tcg_temp_new();
3236 - TCGv t1 = tcg_temp_new();
3237 - TCGv t2 = tcg_temp_new();
3238 - TCGv t3 = tcg_temp_new();
3239 - TCGv s3 = tcg_temp_new();
3240 - TCGv s2 = tcg_temp_new();
3241 - TCGv s1 = tcg_temp_new();
3242 - TCGv s0 = tcg_temp_new();
3235 + TCGv_i32 t0 = tcg_temp_new_i32();
3236 + TCGv_i32 t1 = tcg_temp_new_i32();
3237 + TCGv_i32 t2 = tcg_temp_new_i32();
3238 + TCGv_i32 t3 = tcg_temp_new_i32();
3239 + TCGv_i32 s3 = tcg_temp_new_i32();
3240 + TCGv_i32 s2 = tcg_temp_new_i32();
3241 + TCGv_i32 s1 = tcg_temp_new_i32();
3242 + TCGv_i32 s0 = tcg_temp_new_i32();
3243
3244 gen_load_mxu_gpr(t1, XRb);
3245 - tcg_gen_extract_tl(t0, t1, 0, 16);
3246 - tcg_gen_extract_tl(t1, t1, 16, 16);
3245 + tcg_gen_extract_i32(t0, t1, 0, 16);
3246 + tcg_gen_extract_i32(t1, t1, 16, 16);
3247
3248 gen_load_mxu_gpr(t3, XRc);
3249 - tcg_gen_extract_tl(t2, t3, 0, 16);
3250 - tcg_gen_extract_tl(t3, t3, 16, 16);
3249 + tcg_gen_extract_i32(t2, t3, 0, 16);
3250 + tcg_gen_extract_i32(t3, t3, 16, 16);
3251
3252 switch (aptn2) {
3253 case MXU_APTN2_AA: /* lop +, rop + */
3254 - tcg_gen_add_tl(s3, t1, t3);
3255 - tcg_gen_add_tl(s2, t0, t2);
3256 - tcg_gen_add_tl(s1, t1, t3);
3257 - tcg_gen_add_tl(s0, t0, t2);
3254 + tcg_gen_add_i32(s3, t1, t3);
3255 + tcg_gen_add_i32(s2, t0, t2);
3256 + tcg_gen_add_i32(s1, t1, t3);
3257 + tcg_gen_add_i32(s0, t0, t2);
3258 break;
3259 case MXU_APTN2_AS: /* lop +, rop - */
3260 - tcg_gen_sub_tl(s3, t1, t3);
3261 - tcg_gen_sub_tl(s2, t0, t2);
3262 - tcg_gen_add_tl(s1, t1, t3);
3263 - tcg_gen_add_tl(s0, t0, t2);
3260 + tcg_gen_sub_i32(s3, t1, t3);
3261 + tcg_gen_sub_i32(s2, t0, t2);
3262 + tcg_gen_add_i32(s1, t1, t3);
3263 + tcg_gen_add_i32(s0, t0, t2);
3264 break;
3265 case MXU_APTN2_SA: /* lop -, rop + */
3266 - tcg_gen_add_tl(s3, t1, t3);
3267 - tcg_gen_add_tl(s2, t0, t2);
3268 - tcg_gen_sub_tl(s1, t1, t3);
3269 - tcg_gen_sub_tl(s0, t0, t2);
3266 + tcg_gen_add_i32(s3, t1, t3);
3267 + tcg_gen_add_i32(s2, t0, t2);
3268 + tcg_gen_sub_i32(s1, t1, t3);
3269 + tcg_gen_sub_i32(s0, t0, t2);
3270 break;
3271 case MXU_APTN2_SS: /* lop -, rop - */
3272 - tcg_gen_sub_tl(s3, t1, t3);
3273 - tcg_gen_sub_tl(s2, t0, t2);
3274 - tcg_gen_sub_tl(s1, t1, t3);
3275 - tcg_gen_sub_tl(s0, t0, t2);
3272 + tcg_gen_sub_i32(s3, t1, t3);
3273 + tcg_gen_sub_i32(s2, t0, t2);
3274 + tcg_gen_sub_i32(s1, t1, t3);
3275 + tcg_gen_sub_i32(s0, t0, t2);
3276 break;
3277 }
3278
3279 if (XRa != 0) {
3280 - tcg_gen_add_tl(t0, mxu_gpr[XRa - 1], s0);
3281 - tcg_gen_extract_tl(t0, t0, 0, 16);
3282 - tcg_gen_extract_tl(t1, mxu_gpr[XRa - 1], 16, 16);
3283 - tcg_gen_add_tl(t1, t1, s1);
3284 - tcg_gen_shli_tl(t1, t1, 16);
3285 - tcg_gen_or_tl(mxu_gpr[XRa - 1], t1, t0);
3280 + tcg_gen_add_i32(t0, mxu_gpr[XRa - 1], s0);
3281 + tcg_gen_extract_i32(t0, t0, 0, 16);
3282 + tcg_gen_extract_i32(t1, mxu_gpr[XRa - 1], 16, 16);
3283 + tcg_gen_add_i32(t1, t1, s1);
3284 + tcg_gen_shli_i32(t1, t1, 16);
3285 + tcg_gen_or_i32(mxu_gpr[XRa - 1], t1, t0);
3286 }
3287
3288 if (XRd != 0) {
3289 - tcg_gen_add_tl(t0, mxu_gpr[XRd - 1], s2);
3290 - tcg_gen_extract_tl(t0, t0, 0, 16);
3291 - tcg_gen_extract_tl(t1, mxu_gpr[XRd - 1], 16, 16);
3292 - tcg_gen_add_tl(t1, t1, s3);
3293 - tcg_gen_shli_tl(t1, t1, 16);
3294 - tcg_gen_or_tl(mxu_gpr[XRd - 1], t1, t0);
3289 + tcg_gen_add_i32(t0, mxu_gpr[XRd - 1], s2);
3290 + tcg_gen_extract_i32(t0, t0, 0, 16);
3291 + tcg_gen_extract_i32(t1, mxu_gpr[XRd - 1], 16, 16);
3292 + tcg_gen_add_i32(t1, t1, s3);
3293 + tcg_gen_shli_i32(t1, t1, 16);
3294 + tcg_gen_or_i32(mxu_gpr[XRd - 1], t1, t0);
3295 }
3296 }
3297
@@ -3309,58 +3309,58 @@ static void gen_mxu_q16accm(DisasContext *ctx)
3309 XRb = extract32(ctx->opcode, 10, 4);
3310 XRa = extract32(ctx->opcode, 6, 4);
3311
3312 - TCGv t0 = tcg_temp_new();
3313 - TCGv t1 = tcg_temp_new();
3314 - TCGv t2 = tcg_temp_new();
3315 - TCGv t3 = tcg_temp_new();
3312 + TCGv_i32 t0 = tcg_temp_new_i32();
3313 + TCGv_i32 t1 = tcg_temp_new_i32();
3314 + TCGv_i32 t2 = tcg_temp_new_i32();
3315 + TCGv_i32 t3 = tcg_temp_new_i32();
3316
3317 gen_load_mxu_gpr(t2, XRb);
3318 gen_load_mxu_gpr(t3, XRc);
3319
3320 if (XRa != 0) {
3321 - TCGv a0 = tcg_temp_new();
3322 - TCGv a1 = tcg_temp_new();
3321 + TCGv_i32 a0 = tcg_temp_new_i32();
3322 + TCGv_i32 a1 = tcg_temp_new_i32();
3323
3324 - tcg_gen_extract_tl(t0, t2, 0, 16);
3325 - tcg_gen_extract_tl(t1, t2, 16, 16);
3324 + tcg_gen_extract_i32(t0, t2, 0, 16);
3325 + tcg_gen_extract_i32(t1, t2, 16, 16);
3326
3327 gen_load_mxu_gpr(a1, XRa);
3328 - tcg_gen_extract_tl(a0, a1, 0, 16);
3329 - tcg_gen_extract_tl(a1, a1, 16, 16);
3328 + tcg_gen_extract_i32(a0, a1, 0, 16);
3329 + tcg_gen_extract_i32(a1, a1, 16, 16);
3330
3331 if (aptn2 & 2) {
3332 - tcg_gen_sub_tl(a0, a0, t0);
3333 - tcg_gen_sub_tl(a1, a1, t1);
3332 + tcg_gen_sub_i32(a0, a0, t0);
3333 + tcg_gen_sub_i32(a1, a1, t1);
3334 } else {
3335 - tcg_gen_add_tl(a0, a0, t0);
3336 - tcg_gen_add_tl(a1, a1, t1);
3335 + tcg_gen_add_i32(a0, a0, t0);
3336 + tcg_gen_add_i32(a1, a1, t1);
3337 }
3338 - tcg_gen_extract_tl(a0, a0, 0, 16);
3339 - tcg_gen_shli_tl(a1, a1, 16);
3340 - tcg_gen_or_tl(mxu_gpr[XRa - 1], a1, a0);
3338 + tcg_gen_extract_i32(a0, a0, 0, 16);
3339 + tcg_gen_shli_i32(a1, a1, 16);
3340 + tcg_gen_or_i32(mxu_gpr[XRa - 1], a1, a0);
3341 }
3342
3343 if (XRd != 0) {
3344 - TCGv a0 = tcg_temp_new();
3345 - TCGv a1 = tcg_temp_new();
3344 + TCGv_i32 a0 = tcg_temp_new_i32();
3345 + TCGv_i32 a1 = tcg_temp_new_i32();
3346
3347 - tcg_gen_extract_tl(t0, t3, 0, 16);
3348 - tcg_gen_extract_tl(t1, t3, 16, 16);
3347 + tcg_gen_extract_i32(t0, t3, 0, 16);
3348 + tcg_gen_extract_i32(t1, t3, 16, 16);
3349
3350 gen_load_mxu_gpr(a1, XRd);
3351 - tcg_gen_extract_tl(a0, a1, 0, 16);
3352 - tcg_gen_extract_tl(a1, a1, 16, 16);
3351 + tcg_gen_extract_i32(a0, a1, 0, 16);
3352 + tcg_gen_extract_i32(a1, a1, 16, 16);
3353
3354 if (aptn2 & 1) {
3355 - tcg_gen_sub_tl(a0, a0, t0);
3356 - tcg_gen_sub_tl(a1, a1, t1);
3355 + tcg_gen_sub_i32(a0, a0, t0);
3356 + tcg_gen_sub_i32(a1, a1, t1);
3357 } else {
3358 - tcg_gen_add_tl(a0, a0, t0);
3359 - tcg_gen_add_tl(a1, a1, t1);
3358 + tcg_gen_add_i32(a0, a0, t0);
3359 + tcg_gen_add_i32(a1, a1, t1);
3360 }
3361 - tcg_gen_extract_tl(a0, a0, 0, 16);
3362 - tcg_gen_shli_tl(a1, a1, 16);
3363 - tcg_gen_or_tl(mxu_gpr[XRd - 1], a1, a0);
3361 + tcg_gen_extract_i32(a0, a0, 0, 16);
3362 + tcg_gen_shli_i32(a1, a1, 16);
3363 + tcg_gen_or_i32(mxu_gpr[XRd - 1], a1, a0);
3364 }
3365 }
3366
@@ -3379,33 +3379,33 @@ static void gen_mxu_d16asum(DisasContext *ctx)
3379 XRb = extract32(ctx->opcode, 10, 4);
3380 XRa = extract32(ctx->opcode, 6, 4);
3381
3382 - TCGv t0 = tcg_temp_new();
3383 - TCGv t1 = tcg_temp_new();
3384 - TCGv t2 = tcg_temp_new();
3385 - TCGv t3 = tcg_temp_new();
3382 + TCGv_i32 t0 = tcg_temp_new_i32();
3383 + TCGv_i32 t1 = tcg_temp_new_i32();
3384 + TCGv_i32 t2 = tcg_temp_new_i32();
3385 + TCGv_i32 t3 = tcg_temp_new_i32();
3386
3387 gen_load_mxu_gpr(t2, XRb);
3388 gen_load_mxu_gpr(t3, XRc);
3389
3390 if (XRa != 0) {
3391 - tcg_gen_sextract_tl(t0, t2, 0, 16);
3392 - tcg_gen_sextract_tl(t1, t2, 16, 16);
3393 - tcg_gen_add_tl(t0, t0, t1);
3391 + tcg_gen_sextract_i32(t0, t2, 0, 16);
3392 + tcg_gen_sextract_i32(t1, t2, 16, 16);
3393 + tcg_gen_add_i32(t0, t0, t1);
3394 if (aptn2 & 2) {
3395 - tcg_gen_sub_tl(mxu_gpr[XRa - 1], mxu_gpr[XRa - 1], t0);
3395 + tcg_gen_sub_i32(mxu_gpr[XRa - 1], mxu_gpr[XRa - 1], t0);
3396 } else {
3397 - tcg_gen_add_tl(mxu_gpr[XRa - 1], mxu_gpr[XRa - 1], t0);
3397 + tcg_gen_add_i32(mxu_gpr[XRa - 1], mxu_gpr[XRa - 1], t0);
3398 }
3399 }
3400
3401 if (XRd != 0) {
3402 - tcg_gen_sextract_tl(t0, t3, 0, 16);
3403 - tcg_gen_sextract_tl(t1, t3, 16, 16);
3404 - tcg_gen_add_tl(t0, t0, t1);
3402 + tcg_gen_sextract_i32(t0, t3, 0, 16);
3403 + tcg_gen_sextract_i32(t1, t3, 16, 16);
3404 + tcg_gen_add_i32(t0, t0, t1);
3405 if (aptn2 & 1) {
3406 - tcg_gen_sub_tl(mxu_gpr[XRd - 1], mxu_gpr[XRd - 1], t0);
3406 + tcg_gen_sub_i32(mxu_gpr[XRd - 1], mxu_gpr[XRd - 1], t0);
3407 } else {
3408 - tcg_gen_add_tl(mxu_gpr[XRd - 1], mxu_gpr[XRd - 1], t0);
3408 + tcg_gen_add_i32(mxu_gpr[XRd - 1], mxu_gpr[XRd - 1], t0);
3409 }
3410 }
3411 }
@@ -3428,10 +3428,10 @@ static void gen_mxu_d32add(DisasContext *ctx)
3428 XRb = extract32(ctx->opcode, 10, 4);
3429 XRa = extract32(ctx->opcode, 6, 4);
3430
3431 - TCGv t0 = tcg_temp_new();
3432 - TCGv t1 = tcg_temp_new();
3433 - TCGv t2 = tcg_temp_new();
3434 - TCGv cr = tcg_temp_new();
3431 + TCGv_i32 t0 = tcg_temp_new_i32();
3432 + TCGv_i32 t1 = tcg_temp_new_i32();
3433 + TCGv_i32 t2 = tcg_temp_new_i32();
3434 + TCGv_i32 cr = tcg_temp_new_i32();
3435
3436 if (unlikely(addc > 1)) {
3437 /* opcode incorrect -> do nothing */
@@ -3445,14 +3445,14 @@ static void gen_mxu_d32add(DisasContext *ctx)
3445 gen_load_mxu_gpr(t1, XRc);
3446 gen_load_mxu_cr(cr);
3447 if (XRa != 0) {
3448 - tcg_gen_extract_tl(t2, cr, 31, 1);
3449 - tcg_gen_add_tl(t0, t0, t2);
3450 - tcg_gen_add_tl(mxu_gpr[XRa - 1], mxu_gpr[XRa - 1], t0);
3448 + tcg_gen_extract_i32(t2, cr, 31, 1);
3449 + tcg_gen_add_i32(t0, t0, t2);
3450 + tcg_gen_add_i32(mxu_gpr[XRa - 1], mxu_gpr[XRa - 1], t0);
3451 }
3452 if (XRd != 0) {
3453 - tcg_gen_extract_tl(t2, cr, 30, 1);
3454 - tcg_gen_add_tl(t1, t1, t2);
3455 - tcg_gen_add_tl(mxu_gpr[XRd - 1], mxu_gpr[XRd - 1], t1);
3453 + tcg_gen_extract_i32(t2, cr, 30, 1);
3454 + tcg_gen_add_i32(t1, t1, t2);
3455 + tcg_gen_add_i32(mxu_gpr[XRd - 1], mxu_gpr[XRd - 1], t1);
3456 }
3457 }
3458 } else if (unlikely(XRa == 0 && XRd == 0)) {
@@ -3460,7 +3460,7 @@ static void gen_mxu_d32add(DisasContext *ctx)
3460 } else {
3461 /* common case */
3462 /* FIXME ??? What if XRa == XRd ??? */
3463 - TCGv carry = tcg_temp_new();
3463 + TCGv_i32 carry = tcg_temp_new_i32();
3464
3465 gen_load_mxu_gpr(t0, XRb);
3466 gen_load_mxu_gpr(t1, XRc);
@@ -3468,27 +3468,27 @@ static void gen_mxu_d32add(DisasContext *ctx)
3468 if (XRa != 0) {
3469 if (aptn2 & 2) {
3470 tcg_gen_sub_i32(t2, t0, t1);
3471 - tcg_gen_setcond_tl(TCG_COND_GTU, carry, t0, t1);
3471 + tcg_gen_setcond_i32(TCG_COND_GTU, carry, t0, t1);
3472 } else {
3473 tcg_gen_add_i32(t2, t0, t1);
3474 - tcg_gen_setcond_tl(TCG_COND_GTU, carry, t0, t2);
3474 + tcg_gen_setcond_i32(TCG_COND_GTU, carry, t0, t2);
3475 }
3476 - tcg_gen_andi_tl(cr, cr, 0x7fffffff);
3477 - tcg_gen_shli_tl(carry, carry, 31);
3478 - tcg_gen_or_tl(cr, cr, carry);
3476 + tcg_gen_andi_i32(cr, cr, 0x7fffffff);
3477 + tcg_gen_shli_i32(carry, carry, 31);
3478 + tcg_gen_or_i32(cr, cr, carry);
3479 gen_store_mxu_gpr(t2, XRa);
3480 }
3481 if (XRd != 0) {
3482 if (aptn2 & 1) {
3483 tcg_gen_sub_i32(t2, t0, t1);
3484 - tcg_gen_setcond_tl(TCG_COND_GTU, carry, t0, t1);
3484 + tcg_gen_setcond_i32(TCG_COND_GTU, carry, t0, t1);
3485 } else {
3486 tcg_gen_add_i32(t2, t0, t1);
3487 - tcg_gen_setcond_tl(TCG_COND_GTU, carry, t0, t2);
3487 + tcg_gen_setcond_i32(TCG_COND_GTU, carry, t0, t2);
3488 }
3489 - tcg_gen_andi_tl(cr, cr, 0xbfffffff);
3490 - tcg_gen_shli_tl(carry, carry, 30);
3491 - tcg_gen_or_tl(cr, cr, carry);
3489 + tcg_gen_andi_i32(cr, cr, 0xbfffffff);
3490 + tcg_gen_shli_i32(carry, carry, 30);
3491 + tcg_gen_or_i32(cr, cr, carry);
3492 gen_store_mxu_gpr(t2, XRd);
3493 }
3494 gen_store_mxu_cr(cr);
@@ -3509,9 +3509,9 @@ static void gen_mxu_d32acc(DisasContext *ctx)
3509 XRb = extract32(ctx->opcode, 10, 4);
3510 XRa = extract32(ctx->opcode, 6, 4);
3511
3512 - TCGv t0 = tcg_temp_new();
3513 - TCGv t1 = tcg_temp_new();
3514 - TCGv t2 = tcg_temp_new();
3512 + TCGv_i32 t0 = tcg_temp_new_i32();
3513 + TCGv_i32 t1 = tcg_temp_new_i32();
3514 + TCGv_i32 t2 = tcg_temp_new_i32();
3515
3516 if (unlikely(XRa == 0 && XRd == 0)) {
3517 /* destinations are zero register -> do nothing */
@@ -3521,19 +3521,19 @@ static void gen_mxu_d32acc(DisasContext *ctx)
3521 gen_load_mxu_gpr(t1, XRc);
3522 if (XRa != 0) {
3523 if (aptn2 & 2) {
3524 - tcg_gen_sub_tl(t2, t0, t1);
3524 + tcg_gen_sub_i32(t2, t0, t1);
3525 } else {
3526 - tcg_gen_add_tl(t2, t0, t1);
3526 + tcg_gen_add_i32(t2, t0, t1);
3527 }
3528 - tcg_gen_add_tl(mxu_gpr[XRa - 1], mxu_gpr[XRa - 1], t2);
3528 + tcg_gen_add_i32(mxu_gpr[XRa - 1], mxu_gpr[XRa - 1], t2);
3529 }
3530 if (XRd != 0) {
3531 if (aptn2 & 1) {
3532 - tcg_gen_sub_tl(t2, t0, t1);
3532 + tcg_gen_sub_i32(t2, t0, t1);
3533 } else {
3534 - tcg_gen_add_tl(t2, t0, t1);
3534 + tcg_gen_add_i32(t2, t0, t1);
3535 }
3536 - tcg_gen_add_tl(mxu_gpr[XRd - 1], mxu_gpr[XRd - 1], t2);
3536 + tcg_gen_add_i32(mxu_gpr[XRd - 1], mxu_gpr[XRd - 1], t2);
3537 }
3538 }
3539 }
@@ -3552,9 +3552,9 @@ static void gen_mxu_d32accm(DisasContext *ctx)
3552 XRb = extract32(ctx->opcode, 10, 4);
3553 XRa = extract32(ctx->opcode, 6, 4);
3554
3555 - TCGv t0 = tcg_temp_new();
3556 - TCGv t1 = tcg_temp_new();
3557 - TCGv t2 = tcg_temp_new();
3555 + TCGv_i32 t0 = tcg_temp_new_i32();
3556 + TCGv_i32 t1 = tcg_temp_new_i32();
3557 + TCGv_i32 t2 = tcg_temp_new_i32();
3558
3559 if (unlikely(XRa == 0 && XRd == 0)) {
3560 /* destinations are zero register -> do nothing */
@@ -3563,19 +3563,19 @@ static void gen_mxu_d32accm(DisasContext *ctx)
3563 gen_load_mxu_gpr(t0, XRb);
3564 gen_load_mxu_gpr(t1, XRc);
3565 if (XRa != 0) {
3566 - tcg_gen_add_tl(t2, t0, t1);
3566 + tcg_gen_add_i32(t2, t0, t1);
3567 if (aptn2 & 2) {
3568 - tcg_gen_sub_tl(mxu_gpr[XRa - 1], mxu_gpr[XRa - 1], t2);
3568 + tcg_gen_sub_i32(mxu_gpr[XRa - 1], mxu_gpr[XRa - 1], t2);
3569 } else {
3570 - tcg_gen_add_tl(mxu_gpr[XRa - 1], mxu_gpr[XRa - 1], t2);
3570 + tcg_gen_add_i32(mxu_gpr[XRa - 1], mxu_gpr[XRa - 1], t2);
3571 }
3572 }
3573 if (XRd != 0) {
3574 - tcg_gen_sub_tl(t2, t0, t1);
3574 + tcg_gen_sub_i32(t2, t0, t1);
3575 if (aptn2 & 1) {
3576 - tcg_gen_sub_tl(mxu_gpr[XRd - 1], mxu_gpr[XRd - 1], t2);
3576 + tcg_gen_sub_i32(mxu_gpr[XRd - 1], mxu_gpr[XRd - 1], t2);
3577 } else {
3578 - tcg_gen_add_tl(mxu_gpr[XRd - 1], mxu_gpr[XRd - 1], t2);
3578 + tcg_gen_add_i32(mxu_gpr[XRd - 1], mxu_gpr[XRd - 1], t2);
3579 }
3580 }
3581 }
@@ -3595,8 +3595,8 @@ static void gen_mxu_d32asum(DisasContext *ctx)
3595 XRb = extract32(ctx->opcode, 10, 4);
3596 XRa = extract32(ctx->opcode, 6, 4);
3597
3598 - TCGv t0 = tcg_temp_new();
3599 - TCGv t1 = tcg_temp_new();
3598 + TCGv_i32 t0 = tcg_temp_new_i32();
3599 + TCGv_i32 t1 = tcg_temp_new_i32();
3600
3601 if (unlikely(XRa == 0 && XRd == 0)) {
3602 /* destinations are zero register -> do nothing */
@@ -3606,16 +3606,16 @@ static void gen_mxu_d32asum(DisasContext *ctx)
3606 gen_load_mxu_gpr(t1, XRc);
3607 if (XRa != 0) {
3608 if (aptn2 & 2) {
3609 - tcg_gen_sub_tl(mxu_gpr[XRa - 1], mxu_gpr[XRa - 1], t0);
3609 + tcg_gen_sub_i32(mxu_gpr[XRa - 1], mxu_gpr[XRa - 1], t0);
3610 } else {
3611 - tcg_gen_add_tl(mxu_gpr[XRa - 1], mxu_gpr[XRa - 1], t0);
3611 + tcg_gen_add_i32(mxu_gpr[XRa - 1], mxu_gpr[XRa - 1], t0);
3612 }
3613 }
3614 if (XRd != 0) {
3615 if (aptn2 & 1) {
3616 - tcg_gen_sub_tl(mxu_gpr[XRd - 1], mxu_gpr[XRd - 1], t1);
3616 + tcg_gen_sub_i32(mxu_gpr[XRd - 1], mxu_gpr[XRd - 1], t1);
3617 } else {
3618 - tcg_gen_add_tl(mxu_gpr[XRd - 1], mxu_gpr[XRd - 1], t1);
3618 + tcg_gen_add_i32(mxu_gpr[XRd - 1], mxu_gpr[XRd - 1], t1);
3619 }
3620 }
3621 }
@@ -3638,13 +3638,13 @@ static void gen_mxu_d32asum(DisasContext *ctx)
3638 */
3639 static void gen_mxu_s32extr(DisasContext *ctx)
3640 {
3641 - TCGv t0, t1, t2, t3;
3641 + TCGv_i32 t0, t1, t2, t3;
3642 uint32_t XRa, XRd, rs, bits5;
3643
3644 - t0 = tcg_temp_new();
3645 - t1 = tcg_temp_new();
3646 - t2 = tcg_temp_new();
3647 - t3 = tcg_temp_new();
3644 + t0 = tcg_temp_new_i32();
3645 + t1 = tcg_temp_new_i32();
3646 + t2 = tcg_temp_new_i32();
3647 + t3 = tcg_temp_new_i32();
3648
3649 XRa = extract32(ctx->opcode, 6, 4);
3650 XRd = extract32(ctx->opcode, 10, 4);
@@ -3660,23 +3660,23 @@ static void gen_mxu_s32extr(DisasContext *ctx)
3660 gen_load_mxu_gpr(t0, XRd);
3661 gen_load_mxu_gpr(t1, XRa);
3662 gen_load_gpr(t2, rs);
3663 - tcg_gen_andi_tl(t2, t2, 0x1f);
3664 - tcg_gen_subfi_tl(t2, 32, t2);
3665 - tcg_gen_brcondi_tl(TCG_COND_GE, t2, bits5, l_xra_only);
3666 - tcg_gen_subfi_tl(t2, bits5, t2);
3667 - tcg_gen_subfi_tl(t3, 32, t2);
3668 - tcg_gen_shr_tl(t0, t0, t3);
3669 - tcg_gen_shl_tl(t1, t1, t2);
3670 - tcg_gen_or_tl(t0, t0, t1);
3663 + tcg_gen_andi_i32(t2, t2, 0x1f);
3664 + tcg_gen_subfi_i32(t2, 32, t2);
3665 + tcg_gen_brcondi_i32(TCG_COND_GE, t2, bits5, l_xra_only);
3666 + tcg_gen_subfi_i32(t2, bits5, t2);
3667 + tcg_gen_subfi_i32(t3, 32, t2);
3668 + tcg_gen_shr_i32(t0, t0, t3);
3669 + tcg_gen_shl_i32(t1, t1, t2);
3670 + tcg_gen_or_i32(t0, t0, t1);
3671 tcg_gen_br(l_done);
3672 gen_set_label(l_xra_only);
3673 - tcg_gen_subi_tl(t2, t2, bits5);
3674 - tcg_gen_shr_tl(t0, t1, t2);
3673 + tcg_gen_subi_i32(t2, t2, bits5);
3674 + tcg_gen_shr_i32(t0, t1, t2);
3675 gen_set_label(l_done);
3676 - tcg_gen_extract_tl(t0, t0, 0, bits5);
3676 + tcg_gen_extract_i32(t0, t0, 0, bits5);
3677 } else {
3678 /* unspecified behavior but matches tests on real hardware*/
3679 - tcg_gen_movi_tl(t0, 0);
3679 + tcg_gen_movi_i32(t0, 0);
3680 }
3681 gen_store_mxu_gpr(t0, XRa);
3682 }
@@ -3688,14 +3688,14 @@ static void gen_mxu_s32extr(DisasContext *ctx)
3688 */
3689 static void gen_mxu_s32extrv(DisasContext *ctx)
3690 {
3691 - TCGv t0, t1, t2, t3, t4;
3691 + TCGv_i32 t0, t1, t2, t3, t4;
3692 uint32_t XRa, XRd, rs, rt;
3693
3694 - t0 = tcg_temp_new();
3695 - t1 = tcg_temp_new();
3696 - t2 = tcg_temp_new();
3697 - t3 = tcg_temp_new();
3698 - t4 = tcg_temp_new();
3694 + t0 = tcg_temp_new_i32();
3695 + t1 = tcg_temp_new_i32();
3696 + t2 = tcg_temp_new_i32();
3697 + t3 = tcg_temp_new_i32();
3698 + t4 = tcg_temp_new_i32();
3699 TCGLabel *l_xra_only = gen_new_label();
3700 TCGLabel *l_done = gen_new_label();
3701 TCGLabel *l_zero = gen_new_label();
@@ -3711,32 +3711,32 @@ static void gen_mxu_s32extrv(DisasContext *ctx)
3711 gen_load_mxu_gpr(t1, XRa);
3712 gen_load_gpr(t2, rs);
3713 gen_load_gpr(t4, rt);
3714 - tcg_gen_brcondi_tl(TCG_COND_EQ, t4, 0, l_zero);
3715 - tcg_gen_andi_tl(t2, t2, 0x1f);
3716 - tcg_gen_subfi_tl(t2, 32, t2);
3717 - tcg_gen_brcond_tl(TCG_COND_GE, t2, t4, l_xra_only);
3718 - tcg_gen_sub_tl(t2, t4, t2);
3719 - tcg_gen_subfi_tl(t3, 32, t2);
3720 - tcg_gen_shr_tl(t0, t0, t3);
3721 - tcg_gen_shl_tl(t1, t1, t2);
3722 - tcg_gen_or_tl(t0, t0, t1);
3714 + tcg_gen_brcondi_i32(TCG_COND_EQ, t4, 0, l_zero);
3715 + tcg_gen_andi_i32(t2, t2, 0x1f);
3716 + tcg_gen_subfi_i32(t2, 32, t2);
3717 + tcg_gen_brcond_i32(TCG_COND_GE, t2, t4, l_xra_only);
3718 + tcg_gen_sub_i32(t2, t4, t2);
3719 + tcg_gen_subfi_i32(t3, 32, t2);
3720 + tcg_gen_shr_i32(t0, t0, t3);
3721 + tcg_gen_shl_i32(t1, t1, t2);
3722 + tcg_gen_or_i32(t0, t0, t1);
3723 tcg_gen_br(l_extract);
3724
3725 gen_set_label(l_xra_only);
3726 - tcg_gen_sub_tl(t2, t2, t4);
3727 - tcg_gen_shr_tl(t0, t1, t2);
3726 + tcg_gen_sub_i32(t2, t2, t4);
3727 + tcg_gen_shr_i32(t0, t1, t2);
3728 tcg_gen_br(l_extract);
3729
3730 /* unspecified behavior but matches tests on real hardware*/
3731 gen_set_label(l_zero);
3732 - tcg_gen_movi_tl(t0, 0);
3732 + tcg_gen_movi_i32(t0, 0);
3733 tcg_gen_br(l_done);
3734
3735 /* {XRa} = extract({tmp}, 0, rt) */
3736 gen_set_label(l_extract);
3737 - tcg_gen_subfi_tl(t4, 32, t4);
3738 - tcg_gen_shl_tl(t0, t0, t4);
3739 - tcg_gen_shr_tl(t0, t0, t4);
3737 + tcg_gen_subfi_i32(t4, 32, t4);
3738 + tcg_gen_shl_i32(t0, t0, t4);
3739 + tcg_gen_shr_i32(t0, t0, t4);
3740
3741 gen_set_label(l_done);
3742 gen_store_mxu_gpr(t0, XRa);
@@ -3762,33 +3762,33 @@ static void gen_mxu_s32lui(DisasContext *ctx)
3762 /* destination is zero register -> do nothing */
3763 } else {
3764 uint32_t s16;
3765 - TCGv t0 = tcg_temp_new();
3765 + TCGv_i32 t0 = tcg_temp_new_i32();
3766
3767 switch (optn3) {
3768 case 0:
3769 - tcg_gen_movi_tl(t0, s8);
3769 + tcg_gen_movi_i32(t0, s8);
3770 break;
3771 case 1:
3772 - tcg_gen_movi_tl(t0, s8 << 8);
3772 + tcg_gen_movi_i32(t0, s8 << 8);
3773 break;
3774 case 2:
3775 - tcg_gen_movi_tl(t0, s8 << 16);
3775 + tcg_gen_movi_i32(t0, s8 << 16);
3776 break;
3777 case 3:
3778 - tcg_gen_movi_tl(t0, s8 << 24);
3778 + tcg_gen_movi_i32(t0, s8 << 24);
3779 break;
3780 case 4:
3781 - tcg_gen_movi_tl(t0, (s8 << 16) | s8);
3781 + tcg_gen_movi_i32(t0, (s8 << 16) | s8);
3782 break;
3783 case 5:
3784 - tcg_gen_movi_tl(t0, (s8 << 24) | (s8 << 8));
3784 + tcg_gen_movi_i32(t0, (s8 << 24) | (s8 << 8));
3785 break;
3786 case 6:
3787 s16 = (uint16_t)(int16_t)(int8_t)s8;
3788 - tcg_gen_movi_tl(t0, (s16 << 16) | s16);
3788 + tcg_gen_movi_i32(t0, (s16 << 16) | s16);
3789 break;
3790 case 7:
3791 - tcg_gen_movi_tl(t0, (s8 << 24) | (s8 << 16) | (s8 << 8) | s8);
3791 + tcg_gen_movi_i32(t0, (s8 << 24) | (s8 << 16) | (s8 << 8) | s8);
3792 break;
3793 }
3794 gen_store_mxu_gpr(t0, XRa);
@@ -3816,11 +3816,11 @@ static void gen_mxu_Q16SAT(DisasContext *ctx)
3816 /* destination is zero register -> do nothing */
3817 } else {
3818 /* the most general case */
3819 - TCGv t0 = tcg_temp_new();
3820 - TCGv t1 = tcg_temp_new();
3821 - TCGv t2 = tcg_temp_new();
3819 + TCGv_i32 t0 = tcg_temp_new_i32();
3820 + TCGv_i32 t1 = tcg_temp_new_i32();
3821 + TCGv_i32 t2 = tcg_temp_new_i32();
3822
3823 - tcg_gen_movi_tl(t2, 0);
3823 + tcg_gen_movi_i32(t2, 0);
3824 if (XRb != 0) {
3825 TCGLabel *l_less_hi = gen_new_label();
3826 TCGLabel *l_less_lo = gen_new_label();
@@ -3829,32 +3829,32 @@ static void gen_mxu_Q16SAT(DisasContext *ctx)
3829 TCGLabel *l_greater_lo = gen_new_label();
3830 TCGLabel *l_done = gen_new_label();
3831
3832 - tcg_gen_sari_tl(t0, mxu_gpr[XRb - 1], 16);
3833 - tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0, l_less_hi);
3834 - tcg_gen_brcondi_tl(TCG_COND_GT, t0, 255, l_greater_hi);
3832 + tcg_gen_sari_i32(t0, mxu_gpr[XRb - 1], 16);
3833 + tcg_gen_brcondi_i32(TCG_COND_LT, t0, 0, l_less_hi);
3834 + tcg_gen_brcondi_i32(TCG_COND_GT, t0, 255, l_greater_hi);
3835 tcg_gen_br(l_lo);
3836 gen_set_label(l_less_hi);
3837 - tcg_gen_movi_tl(t0, 0);
3837 + tcg_gen_movi_i32(t0, 0);
3838 tcg_gen_br(l_lo);
3839 gen_set_label(l_greater_hi);
3840 - tcg_gen_movi_tl(t0, 255);
3840 + tcg_gen_movi_i32(t0, 255);
3841
3842 gen_set_label(l_lo);
3843 - tcg_gen_shli_tl(t1, mxu_gpr[XRb - 1], 16);
3844 - tcg_gen_sari_tl(t1, t1, 16);
3845 - tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l_less_lo);
3846 - tcg_gen_brcondi_tl(TCG_COND_GT, t1, 255, l_greater_lo);
3843 + tcg_gen_shli_i32(t1, mxu_gpr[XRb - 1], 16);
3844 + tcg_gen_sari_i32(t1, t1, 16);
3845 + tcg_gen_brcondi_i32(TCG_COND_LT, t1, 0, l_less_lo);
3846 + tcg_gen_brcondi_i32(TCG_COND_GT, t1, 255, l_greater_lo);
3847 tcg_gen_br(l_done);
3848 gen_set_label(l_less_lo);
3849 - tcg_gen_movi_tl(t1, 0);
3849 + tcg_gen_movi_i32(t1, 0);
3850 tcg_gen_br(l_done);
3851 gen_set_label(l_greater_lo);
3852 - tcg_gen_movi_tl(t1, 255);
3852 + tcg_gen_movi_i32(t1, 255);
3853
3854 gen_set_label(l_done);
3855 - tcg_gen_shli_tl(t2, t0, 24);
3856 - tcg_gen_shli_tl(t1, t1, 16);
3857 - tcg_gen_or_tl(t2, t2, t1);
3855 + tcg_gen_shli_i32(t2, t0, 24);
3856 + tcg_gen_shli_i32(t1, t1, 16);
3857 + tcg_gen_or_i32(t2, t2, t1);
3858 }
3859
3860 if (XRc != 0) {
@@ -3865,32 +3865,32 @@ static void gen_mxu_Q16SAT(DisasContext *ctx)
3865 TCGLabel *l_greater_lo = gen_new_label();
3866 TCGLabel *l_done = gen_new_label();
3867
3868 - tcg_gen_sari_tl(t0, mxu_gpr[XRc - 1], 16);
3869 - tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0, l_less_hi);
3870 - tcg_gen_brcondi_tl(TCG_COND_GT, t0, 255, l_greater_hi);
3868 + tcg_gen_sari_i32(t0, mxu_gpr[XRc - 1], 16);
3869 + tcg_gen_brcondi_i32(TCG_COND_LT, t0, 0, l_less_hi);
3870 + tcg_gen_brcondi_i32(TCG_COND_GT, t0, 255, l_greater_hi);
3871 tcg_gen_br(l_lo);
3872 gen_set_label(l_less_hi);
3873 - tcg_gen_movi_tl(t0, 0);
3873 + tcg_gen_movi_i32(t0, 0);
3874 tcg_gen_br(l_lo);
3875 gen_set_label(l_greater_hi);
3876 - tcg_gen_movi_tl(t0, 255);
3876 + tcg_gen_movi_i32(t0, 255);
3877
3878 gen_set_label(l_lo);
3879 - tcg_gen_shli_tl(t1, mxu_gpr[XRc - 1], 16);
3880 - tcg_gen_sari_tl(t1, t1, 16);
3881 - tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l_less_lo);
3882 - tcg_gen_brcondi_tl(TCG_COND_GT, t1, 255, l_greater_lo);
3879 + tcg_gen_shli_i32(t1, mxu_gpr[XRc - 1], 16);
3880 + tcg_gen_sari_i32(t1, t1, 16);
3881 + tcg_gen_brcondi_i32(TCG_COND_LT, t1, 0, l_less_lo);
3882 + tcg_gen_brcondi_i32(TCG_COND_GT, t1, 255, l_greater_lo);
3883 tcg_gen_br(l_done);
3884 gen_set_label(l_less_lo);
3885 - tcg_gen_movi_tl(t1, 0);
3885 + tcg_gen_movi_i32(t1, 0);
3886 tcg_gen_br(l_done);
3887 gen_set_label(l_greater_lo);
3888 - tcg_gen_movi_tl(t1, 255);
3888 + tcg_gen_movi_i32(t1, 255);
3889
3890 gen_set_label(l_done);
3891 - tcg_gen_shli_tl(t0, t0, 8);
3892 - tcg_gen_or_tl(t2, t2, t0);
3893 - tcg_gen_or_tl(t2, t2, t1);
3891 + tcg_gen_shli_i32(t0, t0, 8);
3892 + tcg_gen_or_i32(t2, t2, t0);
3893 + tcg_gen_or_i32(t2, t2, t1);
3894 }
3895 gen_store_mxu_gpr(t2, XRa);
3896 }
@@ -3910,11 +3910,11 @@ static void gen_mxu_q16scop(DisasContext *ctx)
3910 XRb = extract32(ctx->opcode, 10, 4);
3911 XRa = extract32(ctx->opcode, 6, 4);
3912
3913 - TCGv t0 = tcg_temp_new();
3914 - TCGv t1 = tcg_temp_new();
3915 - TCGv t2 = tcg_temp_new();
3916 - TCGv t3 = tcg_temp_new();
3917 - TCGv t4 = tcg_temp_new();
3913 + TCGv_i32 t0 = tcg_temp_new_i32();
3914 + TCGv_i32 t1 = tcg_temp_new_i32();
3915 + TCGv_i32 t2 = tcg_temp_new_i32();
3916 + TCGv_i32 t3 = tcg_temp_new_i32();
3917 + TCGv_i32 t4 = tcg_temp_new_i32();
3918
3919 TCGLabel *l_b_hi_lt = gen_new_label();
3920 TCGLabel *l_b_hi_gt = gen_new_label();
@@ -3930,47 +3930,47 @@ static void gen_mxu_q16scop(DisasContext *ctx)
3930 gen_load_mxu_gpr(t0, XRb);
3931 gen_load_mxu_gpr(t1, XRc);
3932
3933 - tcg_gen_sextract_tl(t2, t0, 16, 16);
3934 - tcg_gen_brcondi_tl(TCG_COND_LT, t2, 0, l_b_hi_lt);
3935 - tcg_gen_brcondi_tl(TCG_COND_GT, t2, 0, l_b_hi_gt);
3936 - tcg_gen_movi_tl(t3, 0);
3933 + tcg_gen_sextract_i32(t2, t0, 16, 16);
3934 + tcg_gen_brcondi_i32(TCG_COND_LT, t2, 0, l_b_hi_lt);
3935 + tcg_gen_brcondi_i32(TCG_COND_GT, t2, 0, l_b_hi_gt);
3936 + tcg_gen_movi_i32(t3, 0);
3937 tcg_gen_br(l_b_lo);
3938 gen_set_label(l_b_hi_lt);
3939 - tcg_gen_movi_tl(t3, 0xffff0000);
3939 + tcg_gen_movi_i32(t3, 0xffff0000);
3940 tcg_gen_br(l_b_lo);
3941 gen_set_label(l_b_hi_gt);
3942 - tcg_gen_movi_tl(t3, 0x00010000);
3942 + tcg_gen_movi_i32(t3, 0x00010000);
3943
3944 gen_set_label(l_b_lo);
3945 - tcg_gen_sextract_tl(t2, t0, 0, 16);
3946 - tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l_c_hi);
3947 - tcg_gen_brcondi_tl(TCG_COND_LT, t2, 0, l_b_lo_lt);
3948 - tcg_gen_ori_tl(t3, t3, 0x00000001);
3945 + tcg_gen_sextract_i32(t2, t0, 0, 16);
3946 + tcg_gen_brcondi_i32(TCG_COND_EQ, t2, 0, l_c_hi);
3947 + tcg_gen_brcondi_i32(TCG_COND_LT, t2, 0, l_b_lo_lt);
3948 + tcg_gen_ori_i32(t3, t3, 0x00000001);
3949 tcg_gen_br(l_c_hi);
3950 gen_set_label(l_b_lo_lt);
3951 - tcg_gen_ori_tl(t3, t3, 0x0000ffff);
3951 + tcg_gen_ori_i32(t3, t3, 0x0000ffff);
3952 tcg_gen_br(l_c_hi);
3953
3954 gen_set_label(l_c_hi);
3955 - tcg_gen_sextract_tl(t2, t1, 16, 16);
3956 - tcg_gen_brcondi_tl(TCG_COND_LT, t2, 0, l_c_hi_lt);
3957 - tcg_gen_brcondi_tl(TCG_COND_GT, t2, 0, l_c_hi_gt);
3958 - tcg_gen_movi_tl(t4, 0);
3955 + tcg_gen_sextract_i32(t2, t1, 16, 16);
3956 + tcg_gen_brcondi_i32(TCG_COND_LT, t2, 0, l_c_hi_lt);
3957 + tcg_gen_brcondi_i32(TCG_COND_GT, t2, 0, l_c_hi_gt);
3958 + tcg_gen_movi_i32(t4, 0);
3959 tcg_gen_br(l_c_lo);
3960 gen_set_label(l_c_hi_lt);
3961 - tcg_gen_movi_tl(t4, 0xffff0000);
3961 + tcg_gen_movi_i32(t4, 0xffff0000);
3962 tcg_gen_br(l_c_lo);
3963 gen_set_label(l_c_hi_gt);
3964 - tcg_gen_movi_tl(t4, 0x00010000);
3964 + tcg_gen_movi_i32(t4, 0x00010000);
3965
3966 gen_set_label(l_c_lo);
3967 - tcg_gen_sextract_tl(t2, t1, 0, 16);
3968 - tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l_done);
3969 - tcg_gen_brcondi_tl(TCG_COND_LT, t2, 0, l_c_lo_lt);
3970 - tcg_gen_ori_tl(t4, t4, 0x00000001);
3967 + tcg_gen_sextract_i32(t2, t1, 0, 16);
3968 + tcg_gen_brcondi_i32(TCG_COND_EQ, t2, 0, l_done);
3969 + tcg_gen_brcondi_i32(TCG_COND_LT, t2, 0, l_c_lo_lt);
3970 + tcg_gen_ori_i32(t4, t4, 0x00000001);
3971 tcg_gen_br(l_done);
3972 gen_set_label(l_c_lo_lt);
3973 - tcg_gen_ori_tl(t4, t4, 0x0000ffff);
3973 + tcg_gen_ori_i32(t4, t4, 0x0000ffff);
3974
3975 gen_set_label(l_done);
3976 gen_store_mxu_gpr(t3, XRa);
@@ -3991,62 +3991,62 @@ static void gen_mxu_s32sfl(DisasContext *ctx)
3991 XRa = extract32(ctx->opcode, 6, 4);
3992 ptn2 = extract32(ctx->opcode, 24, 2);
3993
3994 - TCGv t0 = tcg_temp_new();
3995 - TCGv t1 = tcg_temp_new();
3996 - TCGv t2 = tcg_temp_new();
3997 - TCGv t3 = tcg_temp_new();
3994 + TCGv_i32 t0 = tcg_temp_new_i32();
3995 + TCGv_i32 t1 = tcg_temp_new_i32();
3996 + TCGv_i32 t2 = tcg_temp_new_i32();
3997 + TCGv_i32 t3 = tcg_temp_new_i32();
3998
3999 gen_load_mxu_gpr(t0, XRb);
4000 gen_load_mxu_gpr(t1, XRc);
4001
4002 switch (ptn2) {
4003 case 0:
4004 - tcg_gen_andi_tl(t2, t0, 0xff000000);
4005 - tcg_gen_andi_tl(t3, t1, 0x000000ff);
4006 - tcg_gen_deposit_tl(t3, t3, t0, 8, 8);
4007 - tcg_gen_shri_tl(t0, t0, 8);
4008 - tcg_gen_shri_tl(t1, t1, 8);
4009 - tcg_gen_deposit_tl(t3, t3, t0, 24, 8);
4010 - tcg_gen_deposit_tl(t3, t3, t1, 16, 8);
4011 - tcg_gen_shri_tl(t0, t0, 8);
4012 - tcg_gen_shri_tl(t1, t1, 8);
4013 - tcg_gen_deposit_tl(t2, t2, t0, 8, 8);
4014 - tcg_gen_deposit_tl(t2, t2, t1, 0, 8);
4015 - tcg_gen_shri_tl(t1, t1, 8);
4016 - tcg_gen_deposit_tl(t2, t2, t1, 16, 8);
4004 + tcg_gen_andi_i32(t2, t0, 0xff000000);
4005 + tcg_gen_andi_i32(t3, t1, 0x000000ff);
4006 + tcg_gen_deposit_i32(t3, t3, t0, 8, 8);
4007 + tcg_gen_shri_i32(t0, t0, 8);
4008 + tcg_gen_shri_i32(t1, t1, 8);
4009 + tcg_gen_deposit_i32(t3, t3, t0, 24, 8);
4010 + tcg_gen_deposit_i32(t3, t3, t1, 16, 8);
4011 + tcg_gen_shri_i32(t0, t0, 8);
4012 + tcg_gen_shri_i32(t1, t1, 8);
4013 + tcg_gen_deposit_i32(t2, t2, t0, 8, 8);
4014 + tcg_gen_deposit_i32(t2, t2, t1, 0, 8);
4015 + tcg_gen_shri_i32(t1, t1, 8);
4016 + tcg_gen_deposit_i32(t2, t2, t1, 16, 8);
4017 break;
4018 case 1:
4019 - tcg_gen_andi_tl(t2, t0, 0xff000000);
4020 - tcg_gen_andi_tl(t3, t1, 0x000000ff);
4021 - tcg_gen_deposit_tl(t3, t3, t0, 16, 8);
4022 - tcg_gen_shri_tl(t0, t0, 8);
4023 - tcg_gen_shri_tl(t1, t1, 8);
4024 - tcg_gen_deposit_tl(t2, t2, t0, 16, 8);
4025 - tcg_gen_deposit_tl(t2, t2, t1, 0, 8);
4026 - tcg_gen_shri_tl(t0, t0, 8);
4027 - tcg_gen_shri_tl(t1, t1, 8);
4028 - tcg_gen_deposit_tl(t3, t3, t0, 24, 8);
4029 - tcg_gen_deposit_tl(t3, t3, t1, 8, 8);
4030 - tcg_gen_shri_tl(t1, t1, 8);
4031 - tcg_gen_deposit_tl(t2, t2, t1, 8, 8);
4019 + tcg_gen_andi_i32(t2, t0, 0xff000000);
4020 + tcg_gen_andi_i32(t3, t1, 0x000000ff);
4021 + tcg_gen_deposit_i32(t3, t3, t0, 16, 8);
4022 + tcg_gen_shri_i32(t0, t0, 8);
4023 + tcg_gen_shri_i32(t1, t1, 8);
4024 + tcg_gen_deposit_i32(t2, t2, t0, 16, 8);
4025 + tcg_gen_deposit_i32(t2, t2, t1, 0, 8);
4026 + tcg_gen_shri_i32(t0, t0, 8);
4027 + tcg_gen_shri_i32(t1, t1, 8);
4028 + tcg_gen_deposit_i32(t3, t3, t0, 24, 8);
4029 + tcg_gen_deposit_i32(t3, t3, t1, 8, 8);
4030 + tcg_gen_shri_i32(t1, t1, 8);
4031 + tcg_gen_deposit_i32(t2, t2, t1, 8, 8);
4032 break;
4033 case 2:
4034 - tcg_gen_andi_tl(t2, t0, 0xff00ff00);
4035 - tcg_gen_andi_tl(t3, t1, 0x00ff00ff);
4036 - tcg_gen_deposit_tl(t3, t3, t0, 8, 8);
4037 - tcg_gen_shri_tl(t0, t0, 16);
4038 - tcg_gen_shri_tl(t1, t1, 8);
4039 - tcg_gen_deposit_tl(t2, t2, t1, 0, 8);
4040 - tcg_gen_deposit_tl(t3, t3, t0, 24, 8);
4041 - tcg_gen_shri_tl(t1, t1, 16);
4042 - tcg_gen_deposit_tl(t2, t2, t1, 16, 8);
4034 + tcg_gen_andi_i32(t2, t0, 0xff00ff00);
4035 + tcg_gen_andi_i32(t3, t1, 0x00ff00ff);
4036 + tcg_gen_deposit_i32(t3, t3, t0, 8, 8);
4037 + tcg_gen_shri_i32(t0, t0, 16);
4038 + tcg_gen_shri_i32(t1, t1, 8);
4039 + tcg_gen_deposit_i32(t2, t2, t1, 0, 8);
4040 + tcg_gen_deposit_i32(t3, t3, t0, 24, 8);
4041 + tcg_gen_shri_i32(t1, t1, 16);
4042 + tcg_gen_deposit_i32(t2, t2, t1, 16, 8);
4043 break;
4044 case 3:
4045 - tcg_gen_andi_tl(t2, t0, 0xffff0000);
4046 - tcg_gen_andi_tl(t3, t1, 0x0000ffff);
4047 - tcg_gen_shri_tl(t1, t1, 16);
4048 - tcg_gen_deposit_tl(t2, t2, t1, 0, 16);
4049 - tcg_gen_deposit_tl(t3, t3, t0, 16, 16);
4045 + tcg_gen_andi_i32(t2, t0, 0xffff0000);
4046 + tcg_gen_andi_i32(t3, t1, 0x0000ffff);
4047 + tcg_gen_shri_i32(t1, t1, 16);
4048 + tcg_gen_deposit_i32(t2, t2, t1, 0, 16);
4049 + tcg_gen_deposit_i32(t3, t3, t0, 16, 16);
4050 break;
4051 }
4052
@@ -4067,30 +4067,30 @@ static void gen_mxu_q8sad(DisasContext *ctx)
4067 XRb = extract32(ctx->opcode, 10, 4);
4068 XRa = extract32(ctx->opcode, 6, 4);
4069
4070 - TCGv t0 = tcg_temp_new();
4071 - TCGv t1 = tcg_temp_new();
4072 - TCGv t2 = tcg_temp_new();
4073 - TCGv t3 = tcg_temp_new();
4074 - TCGv t4 = tcg_temp_new();
4075 - TCGv t5 = tcg_temp_new();
4070 + TCGv_i32 t0 = tcg_temp_new_i32();
4071 + TCGv_i32 t1 = tcg_temp_new_i32();
4072 + TCGv_i32 t2 = tcg_temp_new_i32();
4073 + TCGv_i32 t3 = tcg_temp_new_i32();
4074 + TCGv_i32 t4 = tcg_temp_new_i32();
4075 + TCGv_i32 t5 = tcg_temp_new_i32();
4076
4077 gen_load_mxu_gpr(t2, XRb);
4078 gen_load_mxu_gpr(t3, XRc);
4079 gen_load_mxu_gpr(t5, XRd);
4080 - tcg_gen_movi_tl(t4, 0);
4080 + tcg_gen_movi_i32(t4, 0);
4081
4082 for (int i = 0; i < 4; i++) {
4083 - tcg_gen_andi_tl(t0, t2, 0xff);
4084 - tcg_gen_andi_tl(t1, t3, 0xff);
4085 - tcg_gen_sub_tl(t0, t0, t1);
4086 - tcg_gen_abs_tl(t0, t0);
4087 - tcg_gen_add_tl(t4, t4, t0);
4083 + tcg_gen_andi_i32(t0, t2, 0xff);
4084 + tcg_gen_andi_i32(t1, t3, 0xff);
4085 + tcg_gen_sub_i32(t0, t0, t1);
4086 + tcg_gen_abs_i32(t0, t0);
4087 + tcg_gen_add_i32(t4, t4, t0);
4088 if (i < 3) {
4089 - tcg_gen_shri_tl(t2, t2, 8);
4090 - tcg_gen_shri_tl(t3, t3, 8);
4089 + tcg_gen_shri_i32(t2, t2, 8);
4090 + tcg_gen_shri_i32(t3, t3, 8);
4091 }
4092 }
4093 - tcg_gen_add_tl(t5, t5, t4);
4093 + tcg_gen_add_i32(t5, t5, t4);
4094 gen_store_mxu_gpr(t4, XRa);
4095 gen_store_mxu_gpr(t5, XRd);
4096 }
@@ -4196,8 +4196,8 @@ static void gen_mxu_S32ALNI(DisasContext *ctx)
4196 /* XRa */
4197 /* */
4198
4199 - TCGv_i32 t0 = tcg_temp_new();
4200 - TCGv_i32 t1 = tcg_temp_new();
4199 + TCGv_i32 t0 = tcg_temp_new_i32();
4200 + TCGv_i32 t1 = tcg_temp_new_i32();
4201
4202 tcg_gen_andi_i32(t0, mxu_gpr[XRb - 1], 0x00FFFFFF);
4203 tcg_gen_shli_i32(t0, t0, 8);
@@ -4219,8 +4219,8 @@ static void gen_mxu_S32ALNI(DisasContext *ctx)
4219 /* XRa */
4220 /* */
4221
4222 - TCGv_i32 t0 = tcg_temp_new();
4223 - TCGv_i32 t1 = tcg_temp_new();
4222 + TCGv_i32 t0 = tcg_temp_new_i32();
4223 + TCGv_i32 t1 = tcg_temp_new_i32();
4224
4225 tcg_gen_andi_i32(t0, mxu_gpr[XRb - 1], 0x0000FFFF);
4226 tcg_gen_shli_i32(t0, t0, 16);
@@ -4242,8 +4242,8 @@ static void gen_mxu_S32ALNI(DisasContext *ctx)
4242 /* XRa */
4243 /* */
4244
4245 - TCGv_i32 t0 = tcg_temp_new();
4246 - TCGv_i32 t1 = tcg_temp_new();
4245 + TCGv_i32 t0 = tcg_temp_new_i32();
4246 + TCGv_i32 t1 = tcg_temp_new_i32();
4247
4248 tcg_gen_andi_i32(t0, mxu_gpr[XRb - 1], 0x000000FF);
4249 tcg_gen_shli_i32(t0, t0, 24);
@@ -4290,13 +4290,13 @@ static void gen_mxu_S32ALN(DisasContext *ctx)
4290 /* destination is zero register -> do nothing */
4291 } else if (unlikely((XRb == 0) && (XRc == 0))) {
4292 /* both operands zero registers -> just set destination to all 0s */
4293 - tcg_gen_movi_tl(mxu_gpr[XRa - 1], 0);
4293 + tcg_gen_movi_i32(mxu_gpr[XRa - 1], 0);
4294 } else {
4295 /* the most general case */
4296 - TCGv t0 = tcg_temp_new();
4297 - TCGv t1 = tcg_temp_new();
4298 - TCGv t2 = tcg_temp_new();
4299 - TCGv t3 = tcg_temp_new();
4296 + TCGv_i32 t0 = tcg_temp_new_i32();
4297 + TCGv_i32 t1 = tcg_temp_new_i32();
4298 + TCGv_i32 t2 = tcg_temp_new_i32();
4299 + TCGv_i32 t3 = tcg_temp_new_i32();
4300 TCGLabel *l_exit = gen_new_label();
4301 TCGLabel *l_b_only = gen_new_label();
4302 TCGLabel *l_c_only = gen_new_label();
@@ -4304,20 +4304,20 @@ static void gen_mxu_S32ALN(DisasContext *ctx)
4304 gen_load_mxu_gpr(t0, XRb);
4305 gen_load_mxu_gpr(t1, XRc);
4306 gen_load_gpr(t2, rs);
4307 - tcg_gen_andi_tl(t2, t2, 0x07);
4307 + tcg_gen_andi_i32(t2, t2, 0x07);
4308
4309 /* do nothing for undefined cases */
4310 - tcg_gen_brcondi_tl(TCG_COND_GE, t2, 5, l_exit);
4310 + tcg_gen_brcondi_i32(TCG_COND_GE, t2, 5, l_exit);
4311
4312 - tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l_b_only);
4313 - tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 4, l_c_only);
4312 + tcg_gen_brcondi_i32(TCG_COND_EQ, t2, 0, l_b_only);
4313 + tcg_gen_brcondi_i32(TCG_COND_EQ, t2, 4, l_c_only);
4314
4315 - tcg_gen_shli_tl(t2, t2, 3);
4316 - tcg_gen_subfi_tl(t3, 32, t2);
4315 + tcg_gen_shli_i32(t2, t2, 3);
4316 + tcg_gen_subfi_i32(t3, 32, t2);
4317
4318 - tcg_gen_shl_tl(t0, t0, t2);
4319 - tcg_gen_shr_tl(t1, t1, t3);
4320 - tcg_gen_or_tl(mxu_gpr[XRa - 1], t0, t1);
4318 + tcg_gen_shl_i32(t0, t0, t2);
4319 + tcg_gen_shr_i32(t1, t1, t3);
4320 + tcg_gen_or_i32(mxu_gpr[XRa - 1], t0, t1);
4321 tcg_gen_br(l_exit);
4322
4323 gen_set_label(l_b_only);
@@ -4359,8 +4359,8 @@ static void gen_mxu_s32madd_sub(DisasContext *ctx, bool sub, bool uns)
4359 } else if (unlikely(XRa == 0 && XRd == 0)) {
4360 /* do nothing because result just dropped */
4361 } else {
4362 - TCGv t0 = tcg_temp_new();
4363 - TCGv t1 = tcg_temp_new();
4362 + TCGv_i32 t0 = tcg_temp_new_i32();
4363 + TCGv_i32 t1 = tcg_temp_new_i32();
4364 TCGv_i64 t2 = tcg_temp_new_i64();
4365 TCGv_i64 t3 = tcg_temp_new_i64();
4366
@@ -4368,18 +4368,18 @@ static void gen_mxu_s32madd_sub(DisasContext *ctx, bool sub, bool uns)
4368 gen_load_gpr(t1, Rc);
4369
4370 if (uns) {
4371 - tcg_gen_extu_tl_i64(t2, t0);
4372 - tcg_gen_extu_tl_i64(t3, t1);
4371 + tcg_gen_extu_i32_i64(t2, t0);
4372 + tcg_gen_extu_i32_i64(t3, t1);
4373 } else {
4374 - tcg_gen_ext_tl_i64(t2, t0);
4375 - tcg_gen_ext_tl_i64(t3, t1);
4374 + tcg_gen_ext_i32_i64(t2, t0);
4375 + tcg_gen_ext_i32_i64(t3, t1);
4376 }
4377 tcg_gen_mul_i64(t2, t2, t3);
4378
4379 gen_load_mxu_gpr(t0, XRa);
4380 gen_load_mxu_gpr(t1, XRd);
4381
4382 - tcg_gen_concat_tl_i64(t3, t1, t0);
4382 + tcg_gen_concat_i32_i64(t3, t1, t0);
4383 if (sub) {
4384 tcg_gen_sub_i64(t3, t3, t2);
4385 } else {
@@ -4388,8 +4388,8 @@ static void gen_mxu_s32madd_sub(DisasContext *ctx, bool sub, bool uns)
4388 gen_move_low32(t1, t3);
4389 gen_move_high32(t0, t3);
4390
4391 - tcg_gen_mov_tl(cpu_HI[0], t0);
4392 - tcg_gen_mov_tl(cpu_LO[0], t1);
4391 + tcg_gen_mov_i32(cpu_HI[0], t0);
4392 + tcg_gen_mov_i32(cpu_LO[0], t1);
4393
4394 gen_store_mxu_gpr(t1, XRd);
4395 gen_store_mxu_gpr(t0, XRa);
@@ -4936,12 +4936,12 @@ bool decode_ase_mxu(DisasContext *ctx, uint32_t insn)
4936 }
4937
4938 {
4939 - TCGv t_mxu_cr = tcg_temp_new();
4939 + TCGv_i32 t_mxu_cr = tcg_temp_new_i32();
4940 TCGLabel *l_exit = gen_new_label();
4941
4942 gen_load_mxu_cr(t_mxu_cr);
4943 - tcg_gen_andi_tl(t_mxu_cr, t_mxu_cr, MXU_CR_MXU_EN);
4944 - tcg_gen_brcondi_tl(TCG_COND_NE, t_mxu_cr, MXU_CR_MXU_EN, l_exit);
4943 + tcg_gen_andi_i32(t_mxu_cr, t_mxu_cr, MXU_CR_MXU_EN);
4944 + tcg_gen_brcondi_i32(TCG_COND_NE, t_mxu_cr, MXU_CR_MXU_EN, l_exit);
4945
4946 switch (opcode) {
4947 case OPC_MXU_S32MADD: