@samitouri / QOSamiQemu / commits / 10059583c7

include/tcg/tcg-op.h: eradicate TARGET_INSN_START_EXTRA_WORDS

This commit removes TARGET_INSN_START_EXTRA_WORDS and force all arch to call the same version of tcg_gen_insn_start, with additional 0 arguments if needed. Since all arch have a single call site (in translate.c), this is as good documentation as having a single define. The notable exception is target/arm, which has two different translate files for 32/64 bits. Since it's the only one, we accept to have two call sites for this. As well, we update parameter type to use uint64_t instead of target_ulong, so it can be called from common code. Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Message-id: 20260219040150.2098396-15-pierrick.bouvier@linaro.org Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

Pierrick Bouvier committed Feb 18, 2026 at 20:01 UTC 10059583c7bfea50c1596310b0639669e93ce1ee
35 files changed +24 -93
include/tcg/tcg-op-common.h
+8
@@ -30,6 +30,14 @@ TCGv_i64 tcg_global_mem_new_i64(TCGv_ptr reg, intptr_t off, const char *name);
30 TCGv_ptr tcg_global_mem_new_ptr(TCGv_ptr reg, intptr_t off, const char *name);
31
32 /* Generic ops. */
33 +static inline void tcg_gen_insn_start(uint64_t pc, uint64_t a1,
34 + uint64_t a2)
35 +{
36 + TCGOp *op = tcg_emit_op(INDEX_op_insn_start, INSN_START_WORDS);
37 + tcg_set_insn_start_param(op, 0, pc);
38 + tcg_set_insn_start_param(op, 1, a1);
39 + tcg_set_insn_start_param(op, 2, a2);
40 +}
41
42 void gen_set_label(TCGLabel *l);
43 void tcg_gen_br(TCGLabel *l);
include/tcg/tcg-op.h
-29
@@ -28,35 +28,6 @@
28 # error Mismatch with insn-start-words.h
29 #endif
30
31 -#if TARGET_INSN_START_EXTRA_WORDS == 0
32 -static inline void tcg_gen_insn_start(target_ulong pc)
33 -{
34 - TCGOp *op = tcg_emit_op(INDEX_op_insn_start, INSN_START_WORDS);
35 - tcg_set_insn_start_param(op, 0, pc);
36 - tcg_set_insn_start_param(op, 1, 0);
37 - tcg_set_insn_start_param(op, 2, 0);
38 -}
39 -#elif TARGET_INSN_START_EXTRA_WORDS == 1
40 -static inline void tcg_gen_insn_start(target_ulong pc, target_ulong a1)
41 -{
42 - TCGOp *op = tcg_emit_op(INDEX_op_insn_start, INSN_START_WORDS);
43 - tcg_set_insn_start_param(op, 0, pc);
44 - tcg_set_insn_start_param(op, 1, a1);
45 - tcg_set_insn_start_param(op, 2, 0);
46 -}
47 -#elif TARGET_INSN_START_EXTRA_WORDS == 2
48 -static inline void tcg_gen_insn_start(target_ulong pc, target_ulong a1,
49 - target_ulong a2)
50 -{
51 - TCGOp *op = tcg_emit_op(INDEX_op_insn_start, INSN_START_WORDS);
52 - tcg_set_insn_start_param(op, 0, pc);
53 - tcg_set_insn_start_param(op, 1, a1);
54 - tcg_set_insn_start_param(op, 2, a2);
55 -}
56 -#else
57 -#error Unhandled TARGET_INSN_START_EXTRA_WORDS value
58 -#endif
59 -
31 #if TARGET_LONG_BITS == 32
32 typedef TCGv_i32 TCGv;
33 #define tcg_temp_new() tcg_temp_new_i32()
target/alpha/cpu-param.h
-2
@@ -24,6 +24,4 @@
24 # define TARGET_VIRT_ADDR_SPACE_BITS (30 + TARGET_PAGE_BITS)
25 #endif
26
27 -#define TARGET_INSN_START_EXTRA_WORDS 0
28 -
27 #endif
target/alpha/translate.c
+2 -2
@@ -2899,9 +2899,9 @@ static void alpha_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu)
2899 DisasContext *ctx = container_of(dcbase, DisasContext, base);
2900
2901 if (ctx->pcrel) {
2902 - tcg_gen_insn_start(dcbase->pc_next & ~TARGET_PAGE_MASK);
2902 + tcg_gen_insn_start(dcbase->pc_next & ~TARGET_PAGE_MASK, 0, 0);
2903 } else {
2904 - tcg_gen_insn_start(dcbase->pc_next);
2904 + tcg_gen_insn_start(dcbase->pc_next, 0, 0);
2905 }
2906 }
2907
target/arm/cpu-param.h
-7
@@ -32,11 +32,4 @@
32 # define TARGET_PAGE_BITS_LEGACY 10
33 #endif /* !CONFIG_USER_ONLY */
34
35 -/*
36 - * ARM-specific extra insn start words:
37 - * 1: Conditional execution bits
38 - * 2: Partial exception syndrome for data aborts
39 - */
40 -#define TARGET_INSN_START_EXTRA_WORDS 2
41 -
35 #endif
target/avr/cpu-param.h
-2
@@ -25,6 +25,4 @@
25 #define TARGET_PHYS_ADDR_SPACE_BITS 24
26 #define TARGET_VIRT_ADDR_SPACE_BITS 24
27
28 -#define TARGET_INSN_START_EXTRA_WORDS 0
29 -
28 #endif
target/avr/translate.c
+1 -1
@@ -2689,7 +2689,7 @@ static void avr_tr_insn_start(DisasContextBase *dcbase, CPUState *cs)
2689 {
2690 DisasContext *ctx = container_of(dcbase, DisasContext, base);
2691
2692 - tcg_gen_insn_start(ctx->npc);
2692 + tcg_gen_insn_start(ctx->npc, 0, 0);
2693 }
2694
2695 static void avr_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
target/hexagon/cpu-param.h
-2
@@ -23,6 +23,4 @@
23 #define TARGET_PHYS_ADDR_SPACE_BITS 36
24 #define TARGET_VIRT_ADDR_SPACE_BITS 32
25
26 -#define TARGET_INSN_START_EXTRA_WORDS 0
27 -
26 #endif
target/hexagon/translate.c
+1 -1
@@ -998,7 +998,7 @@ static void hexagon_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu)
998 {
999 DisasContext *ctx = container_of(dcbase, DisasContext, base);
1000
1001 - tcg_gen_insn_start(ctx->base.pc_next);
1001 + tcg_gen_insn_start(ctx->base.pc_next, 0, 0);
1002 }
1003
1004 static bool pkt_crosses_page(CPUHexagonState *env, DisasContext *ctx)
target/hppa/cpu-param.h
-2
@@ -19,6 +19,4 @@
19
20 #define TARGET_PAGE_BITS 12
21
22 -#define TARGET_INSN_START_EXTRA_WORDS 2
23 -
22 #endif
target/i386/cpu-param.h
-2
@@ -22,6 +22,4 @@
22 #endif
23 #define TARGET_PAGE_BITS 12
24
25 -#define TARGET_INSN_START_EXTRA_WORDS 1
26 -
25 #endif
target/i386/tcg/translate.c
+1 -1
@@ -3501,7 +3501,7 @@ static void i386_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu)
3501 if (tb_cflags(dcbase->tb) & CF_PCREL) {
3502 pc_arg &= ~TARGET_PAGE_MASK;
3503 }
3504 - tcg_gen_insn_start(pc_arg, dc->cc_op);
3504 + tcg_gen_insn_start(pc_arg, dc->cc_op, 0);
3505 }
3506
3507 static void i386_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
target/loongarch/cpu-param.h
-2
@@ -13,6 +13,4 @@
13
14 #define TARGET_PAGE_BITS 12
15
16 -#define TARGET_INSN_START_EXTRA_WORDS 0
17 -
16 #endif
target/loongarch/tcg/translate.c
+1 -1
@@ -159,7 +159,7 @@ static void loongarch_tr_insn_start(DisasContextBase *dcbase, CPUState *cs)
159 {
160 DisasContext *ctx = container_of(dcbase, DisasContext, base);
161
162 - tcg_gen_insn_start(ctx->base.pc_next);
162 + tcg_gen_insn_start(ctx->base.pc_next, 0, 0);
163 }
164
165 /*
target/m68k/cpu-param.h
-2
@@ -17,6 +17,4 @@
17 #define TARGET_PHYS_ADDR_SPACE_BITS 32
18 #define TARGET_VIRT_ADDR_SPACE_BITS 32
19
20 -#define TARGET_INSN_START_EXTRA_WORDS 1
21 -
20 #endif
target/m68k/translate.c
+1 -1
@@ -6041,7 +6041,7 @@ static void m68k_tr_tb_start(DisasContextBase *dcbase, CPUState *cpu)
6041 static void m68k_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu)
6042 {
6043 DisasContext *dc = container_of(dcbase, DisasContext, base);
6044 - tcg_gen_insn_start(dc->base.pc_next, dc->cc_op);
6044 + tcg_gen_insn_start(dc->base.pc_next, dc->cc_op, 0);
6045 }
6046
6047 static void m68k_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
target/microblaze/cpu-param.h
-2
@@ -27,6 +27,4 @@
27 /* FIXME: MB uses variable pages down to 1K but linux only uses 4k. */
28 #define TARGET_PAGE_BITS 12
29
30 -#define TARGET_INSN_START_EXTRA_WORDS 1
31 -
30 #endif
target/microblaze/translate.c
+1 -1
@@ -1630,7 +1630,7 @@ static void mb_tr_insn_start(DisasContextBase *dcb, CPUState *cs)
1630 {
1631 DisasContext *dc = container_of(dcb, DisasContext, base);
1632
1633 - tcg_gen_insn_start(dc->base.pc_next, dc->tb_flags & ~MSR_TB_MASK);
1633 + tcg_gen_insn_start(dc->base.pc_next, dc->tb_flags & ~MSR_TB_MASK, 0);
1634 }
1635
1636 static void mb_tr_translate_insn(DisasContextBase *dcb, CPUState *cs)
target/mips/cpu-param.h
-2
@@ -20,6 +20,4 @@
20 #endif
21 #define TARGET_PAGE_BITS 12
22
23 -#define TARGET_INSN_START_EXTRA_WORDS 2
24 -
23 #endif
target/or1k/cpu-param.h
-2
@@ -12,6 +12,4 @@
12 #define TARGET_PHYS_ADDR_SPACE_BITS 32
13 #define TARGET_VIRT_ADDR_SPACE_BITS 32
14
15 -#define TARGET_INSN_START_EXTRA_WORDS 1
16 -
15 #endif
target/or1k/translate.c
+1 -1
@@ -1552,7 +1552,7 @@ static void openrisc_tr_insn_start(DisasContextBase *dcbase, CPUState *cs)
1552 DisasContext *dc = container_of(dcbase, DisasContext, base);
1553
1554 tcg_gen_insn_start(dc->base.pc_next, (dc->delayed_branch ? 1 : 0)
1555 - | (dc->base.num_insns > 1 ? 2 : 0));
1555 + | (dc->base.num_insns > 1 ? 2 : 0), 0);
1556 }
1557
1558 static void openrisc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
target/ppc/cpu-param.h
-2
@@ -37,6 +37,4 @@
37 # define TARGET_PAGE_BITS 12
38 #endif
39
40 -#define TARGET_INSN_START_EXTRA_WORDS 0
41 -
40 #endif
target/ppc/translate.c
+1 -1
@@ -6575,7 +6575,7 @@ static void ppc_tr_tb_start(DisasContextBase *db, CPUState *cs)
6575
6576 static void ppc_tr_insn_start(DisasContextBase *dcbase, CPUState *cs)
6577 {
6578 - tcg_gen_insn_start(dcbase->pc_next);
6578 + tcg_gen_insn_start(dcbase->pc_next, 0, 0);
6579 }
6580
6581 static bool is_prefix_insn(DisasContext *ctx, uint32_t insn)
target/riscv/cpu-param.h
-7
@@ -17,13 +17,6 @@
17 #endif
18 #define TARGET_PAGE_BITS 12 /* 4 KiB Pages */
19
20 -/*
21 - * RISC-V-specific extra insn start words:
22 - * 1: Original instruction opcode
23 - * 2: more information about instruction
24 - */
25 -#define TARGET_INSN_START_EXTRA_WORDS 2
26 -
20 /*
21 * The current MMU Modes are:
22 * - U mode 0b000
target/rx/cpu-param.h
-2
@@ -24,6 +24,4 @@
24 #define TARGET_PHYS_ADDR_SPACE_BITS 32
25 #define TARGET_VIRT_ADDR_SPACE_BITS 32
26
27 -#define TARGET_INSN_START_EXTRA_WORDS 0
28 -
27 #endif
target/rx/translate.c
+1 -1
@@ -2217,7 +2217,7 @@ static void rx_tr_insn_start(DisasContextBase *dcbase, CPUState *cs)
2217 {
2218 DisasContext *ctx = container_of(dcbase, DisasContext, base);
2219
2220 - tcg_gen_insn_start(ctx->base.pc_next);
2220 + tcg_gen_insn_start(ctx->base.pc_next, 0, 0);
2221 }
2222
2223 static void rx_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
target/s390x/cpu-param.h
-2
@@ -12,6 +12,4 @@
12 #define TARGET_PHYS_ADDR_SPACE_BITS 64
13 #define TARGET_VIRT_ADDR_SPACE_BITS 64
14
15 -#define TARGET_INSN_START_EXTRA_WORDS 2
16 -
15 #endif
target/sh4/cpu-param.h
-2
@@ -16,6 +16,4 @@
16 # define TARGET_VIRT_ADDR_SPACE_BITS 32
17 #endif
18
19 -#define TARGET_INSN_START_EXTRA_WORDS 1
20 -
19 #endif
target/sh4/translate.c
+2 -2
@@ -2181,7 +2181,7 @@ static void decode_gusa(DisasContext *ctx, CPUSH4State *env)
2181 * tb->icount * insn_start.
2182 */
2183 for (i = 1; i < max_insns; ++i) {
2184 - tcg_gen_insn_start(pc + i * 2, ctx->envflags);
2184 + tcg_gen_insn_start(pc + i * 2, ctx->envflags, 0);
2185 ctx->base.insn_start = tcg_last_op();
2186 }
2187 }
@@ -2241,7 +2241,7 @@ static void sh4_tr_insn_start(DisasContextBase *dcbase, CPUState *cs)
2241 {
2242 DisasContext *ctx = container_of(dcbase, DisasContext, base);
2243
2244 - tcg_gen_insn_start(ctx->base.pc_next, ctx->envflags);
2244 + tcg_gen_insn_start(ctx->base.pc_next, ctx->envflags, 0);
2245 }
2246
2247 static void sh4_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
target/sparc/cpu-param.h
-2
@@ -21,6 +21,4 @@
21 # define TARGET_VIRT_ADDR_SPACE_BITS 32
22 #endif
23
24 -#define TARGET_INSN_START_EXTRA_WORDS 1
25 -
24 #endif
target/sparc/translate.c
+1 -1
@@ -5735,7 +5735,7 @@ static void sparc_tr_insn_start(DisasContextBase *dcbase, CPUState *cs)
5735 g_assert_not_reached();
5736 }
5737 }
5738 - tcg_gen_insn_start(dc->pc, npc);
5738 + tcg_gen_insn_start(dc->pc, npc, 0);
5739 }
5740
5741 static void sparc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
target/tricore/cpu-param.h
-2
@@ -12,6 +12,4 @@
12 #define TARGET_PHYS_ADDR_SPACE_BITS 32
13 #define TARGET_VIRT_ADDR_SPACE_BITS 32
14
15 -#define TARGET_INSN_START_EXTRA_WORDS 0
16 -
15 #endif
target/tricore/translate.c
+1 -1
@@ -8410,7 +8410,7 @@ static void tricore_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu)
8410 {
8411 DisasContext *ctx = container_of(dcbase, DisasContext, base);
8412
8413 - tcg_gen_insn_start(ctx->base.pc_next);
8413 + tcg_gen_insn_start(ctx->base.pc_next, 0, 0);
8414 }
8415
8416 static bool insn_crosses_page(DisasContext *ctx, CPUTriCoreState *env)
target/xtensa/cpu-param.h
-2
@@ -16,6 +16,4 @@
16 #define TARGET_VIRT_ADDR_SPACE_BITS 32
17 #endif
18
19 -#define TARGET_INSN_START_EXTRA_WORDS 0
20 -
19 #endif
target/xtensa/translate.c
+1 -1
@@ -1159,7 +1159,7 @@ static void xtensa_tr_tb_start(DisasContextBase *dcbase, CPUState *cpu)
1159
1160 static void xtensa_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu)
1161 {
1162 - tcg_gen_insn_start(dcbase->pc_next);
1162 + tcg_gen_insn_start(dcbase->pc_next, 0, 0);
1163 }
1164
1165 static void xtensa_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)