@samitouri / QOSamiQemu / commits / 1aa989a176

hw/cxl/events: Updates for rev3.2 general media event record

CXL spec rev3.2 section 8.2.10.2.1.1 Table 8-57, general media event table has updated with following new fields. 1. Advanced Programmable Corrected Memory Error Threshold Event Flags 2. Corrected Memory Error Count at Event 3. Memory Event Sub-Type 4. Support for component ID in the PLDM format. Add updates for the above spec changes in the CXL general media event reporting and QMP command to inject general media event. In order to have one consistent source of references, update all to references for this command to CXL r3.2. Signed-off-by: Shiju Jose <shiju.jose@huawei.com> Acked-by: Markus Armbruster <armbru@redhat.com> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com> Message-Id: <20260205112350.60681-4-Jonathan.Cameron@huawei.com>

Shiju Jose committed Feb 5, 2026 at 11:23 UTC 1aa989a1767f91803493ec05d399f9c96bed3b90
4 files changed +62 -11
hw/mem/cxl_type3.c
+30 -1
@@ -1646,6 +1646,11 @@ static const QemuUUID memory_module_uuid = {
1646 #define CXL_GMER_VALID_RANK BIT(1)
1647 #define CXL_GMER_VALID_DEVICE BIT(2)
1648 #define CXL_GMER_VALID_COMPONENT BIT(3)
1649 +#define CXL_GMER_VALID_COMPONENT_ID_FORMAT BIT(4)
1650 +
1651 +#define CXL_GMER_EV_DESC_UCE BIT(0)
1652 +#define CXL_GMER_EV_DESC_THRESHOLD_EVENT BIT(1)
1653 +#define CXL_GMER_EV_DESC_POISON_LIST_OVERFLOW_EVENT BIT(2)
1654
1655 static int ct3d_qmp_cxl_event_log_enc(CxlEventLog log)
1656 {
@@ -1677,6 +1682,12 @@ void qmp_cxl_inject_general_media_event(const char *path, CxlEventLog log,
1682 bool has_rank, uint8_t rank,
1683 bool has_device, uint32_t device,
1684 const char *component_id,
1685 + bool has_comp_id_pldm,
1686 + bool is_comp_id_pldm,
1687 + bool has_cme_ev_flags,
1688 + uint8_t cme_ev_flags,
1689 + bool has_cme_count, uint32_t cme_count,
1690 + uint8_t sub_type,
1691 Error **errp)
1692 {
1693 Object *obj = object_resolve_path(path, NULL);
@@ -1714,7 +1725,6 @@ void qmp_cxl_inject_general_media_event(const char *path, CxlEventLog log,
1725 has_ld_id, ld_id, has_head_id, head_id);
1726
1727 stq_le_p(&gem.phys_addr, dpa);
1717 - gem.descriptor = descriptor;
1728 gem.type = type;
1729 gem.transaction_type = transaction_type;
1730
@@ -1737,10 +1747,29 @@ void qmp_cxl_inject_general_media_event(const char *path, CxlEventLog log,
1747 strncpy((char *)gem.component_id, component_id,
1748 sizeof(gem.component_id) - 1);
1749 valid_flags |= CXL_GMER_VALID_COMPONENT;
1750 + if (has_comp_id_pldm && is_comp_id_pldm) {
1751 + valid_flags |= CXL_GMER_VALID_COMPONENT_ID_FORMAT;
1752 + }
1753 }
1754
1755 stw_le_p(&gem.validity_flags, valid_flags);
1756
1757 + if (has_cme_ev_flags) {
1758 + gem.cme_ev_flags = cme_ev_flags;
1759 + } else {
1760 + gem.cme_ev_flags = 0;
1761 + }
1762 +
1763 + if (has_cme_count) {
1764 + descriptor |= CXL_GMER_EV_DESC_THRESHOLD_EVENT;
1765 + st24_le_p(gem.cme_count, cme_count);
1766 + } else {
1767 + st24_le_p(gem.cme_count, 0);
1768 + }
1769 + gem.descriptor = descriptor;
1770 +
1771 + gem.sub_type = sub_type;
1772 +
1773 if (cxl_event_insert(cxlds, enc_log, (CXLEventRecordRaw *)&gem)) {
1774 cxl_event_irq_assert(ct3d);
1775 }
hw/mem/cxl_type3_stubs.c
+6
@@ -27,6 +27,12 @@ void qmp_cxl_inject_general_media_event(const char *path, CxlEventLog log,
27 bool has_rank, uint8_t rank,
28 bool has_device, uint32_t device,
29 const char *component_id,
30 + bool has_comp_id_pldm,
31 + bool is_comp_id_pldm,
32 + bool has_cme_ev_flags,
33 + uint8_t cme_ev_flags,
34 + bool has_cme_count, uint32_t cme_count,
35 + uint8_t sub_type,
36 Error **errp) {}
37
38 void qmp_cxl_inject_dram_event(const char *path, CxlEventLog log,
include/hw/cxl/cxl_events.h
+5 -2
@@ -115,10 +115,10 @@ typedef struct CXLEventInterruptPolicy {
115
116 /*
117 * General Media Event Record
118 - * CXL r3.1 Section 8.2.9.2.1.1; Table 8-45
118 + * CXL r3.2 Section 8.2.10.2.1.1; Table 8-57
119 */
120 #define CXL_EVENT_GEN_MED_COMP_ID_SIZE 0x10
121 -#define CXL_EVENT_GEN_MED_RES_SIZE 0x2e
121 +#define CXL_EVENT_GEN_MED_RES_SIZE 0x29
122 typedef struct CXLEventGenMedia {
123 CXLEventRecordHdr hdr;
124 uint64_t phys_addr;
@@ -130,6 +130,9 @@ typedef struct CXLEventGenMedia {
130 uint8_t rank;
131 uint8_t device[3];
132 uint8_t component_id[CXL_EVENT_GEN_MED_COMP_ID_SIZE];
133 + uint8_t cme_ev_flags;
134 + uint8_t cme_count[3];
135 + uint8_t sub_type;
136 uint8_t reserved[CXL_EVENT_GEN_MED_RES_SIZE];
137 } QEMU_PACKED CXLEventGenMedia;
138
qapi/cxl.json
+21 -8
@@ -64,22 +64,22 @@
64 ##
65 # @CXLGeneralMediaEvent:
66 #
67 -# Event record for a General Media Event (CXL r3.0 8.2.9.2.1.1).
67 +# Event record for a General Media Event (CXL r3.2 8.2.10.2.1.1).
68 #
69 # @dpa: Device Physical Address (relative to @path device). Note
70 -# lower bits include some flags. See CXL r3.0 Table 8-43 General
70 +# lower bits include some flags. See CXL r3.2 Table 8-57 General
71 # Media Event Record, Physical Address.
72 #
73 # @descriptor: Memory Event Descriptor with additional memory event
74 -# information. See CXL r3.0 Table 8-43 General Media Event
74 +# information. See CXL r3.2 Table 8-57 General Media Event
75 # Record, Memory Event Descriptor for bit definitions.
76 #
77 -# @type: Type of memory event that occurred. See CXL r3.0 Table 8-43
77 +# @type: Type of memory event that occurred. See CXL r3.2 Table 8-57
78 # General Media Event Record, Memory Event Type for possible
79 # values.
80 #
81 # @transaction-type: Type of first transaction that caused the event
82 -# to occur. See CXL r3.0 Table 8-43 General Media Event Record,
82 +# to occur. See CXL r3-2 Table 8-57 General Media Event Record,
83 # Transaction Type for possible values.
84 #
85 # @channel: The channel of the memory event location. A channel is an
@@ -94,6 +94,16 @@
94 # @component-id: Device specific component identifier for the event.
95 # May describe a field replaceable sub-component of the device.
96 #
97 +# @is-comp-id-pldm: This flag specifies whether the device-specific
98 +# component identifier format follows PLDM.
99 +#
100 +# @cme-ev-flags: Advanced programmable corrected memory error
101 +# threshold event flags.
102 +#
103 +# @cme-count: Corrected memory error count at event.
104 +#
105 +# @sub-type: Memory event sub-type.
106 +#
107 # Since: 8.1
108 ##
109 { 'struct': 'CXLGeneralMediaEvent',
@@ -101,13 +111,16 @@
111 'data': { 'dpa': 'uint64', 'descriptor': 'uint8',
112 'type': 'uint8', 'transaction-type': 'uint8',
113 '*channel': 'uint8', '*rank': 'uint8',
104 - '*device': 'uint32', '*component-id': 'str' } }
114 + '*device': 'uint32', '*component-id': 'str',
115 + '*is-comp-id-pldm':'bool',
116 + '*cme-ev-flags':'uint8', '*cme-count':'uint32',
117 + 'sub-type':'uint8' } }
118
119 ##
120 # @cxl-inject-general-media-event:
121 #
109 -# Inject an event record for a General Media Event (CXL r3.0
110 -# 8.2.9.2.1.1). This event type is reported via one of the event
122 +# Inject an event record for a General Media Event (CXL r3.2
123 +# 8.2.10.2.1.1). This event type is reported via one of the event
124 # logs specified via the log parameter.
125 #
126 # Since: 8.1