Merge tag 'mips-20260520' of https://github.com/philmd/qemu into staging

MIPS patches queue - Remove support for MIPS host - Avoid Coverity complaint in gic_write (CID 1547545) - Add various Octeon integer, multiplier, indexed memory, atomic instructions # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCAAdFiEE+qvnXhKRciHc/Wuy4+MsLN6twN4FAmoOpHwACgkQ4+MsLN6t # wN6lag/8DMO7X2si5SoViaaWdRSeEjyoXRUf+p/Yk55dT0vKWDVZUBBLGjOlox0F # iLa/z104jjppY9vLpbtpg8LKSOUc8JKurAa3DMhYoKpIfwHonGUSNlBIFbqcMECq # BEZQrzhp7trpdpbnPZfwJaFBBg0U++pGS/VJfmFtb4FuSZCKiux/tYj5LMVjVgvb # UEVqvZWJ+WKsEmrEg2DvfrwFBtA/bD14SIK9l3B5ztovms8R1a2ooZvjn9VW9CZA # 2mLy16B78viRGI9XsOqQlrkB2jd5fE8Al/rESPFhDccmPcOyVe9gxcmICfaxfhvK # bwSMk8KRN99ZJ//H7NloJubceKpcLEUfiqfGYtS32dB/KE/pp3fNKBSmOa4Bu/hK # +rBTBg0xV9D9tzCIV0lldSM+NkP3VwhS3vdTnxrGalZmk6fUQxFBwaK6XdXZqTi8 # cE6GuQYivow4+2D9G4yxPU9A0C4wb3nEr7T4lU2gAEvKwapoAbeJpQw/NMudevz7 # t8zJoihOWP66qMUxwuzEBKYzD0fDyeUXFYHmJiHN8392Pxr/Ya3T5YJzLXXcYC0p # 7TPClXS2al+WowWNXtUkXMPHy4KDV/kI9maZxciJ1g61B2+A0qhgbjE+bBDqpoot # wGVv0AVt2bYQvWYcR68uFQNNwmVSfEkHpjoToGaaq5e6DDyxBBY= # =ZXA1 # -----END PGP SIGNATURE----- # gpg: Signature made Thu 21 May 2026 02:21:48 EDT # gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE # gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [full] # Primary key fingerprint: FAAB E75E 1291 7221 DCFD 6BB2 E3E3 2C2C DEAD C0DE * tag 'mips-20260520' of https://github.com/philmd/qemu: (33 commits) target/mips: add Octeon LA* atomic instructions target/mips: add Octeon QMAC instructions target/mips: add Octeon V3MULU instruction target/mips: add Octeon VMM0 instruction target/mips: add Octeon VMULU instruction target/mips: add Octeon MTP instructions target/mips: add Octeon MTM instructions target/mips: add Octeon multiplier state tcg: Introduce tcg_gen_addN_i64 target/mips: add Octeon ZCB and ZCBT instructions tcg: Introduce tcg_zero_i128() target/mips: add Octeon SAAD instruction target/mips: add Octeon SAA instruction target/mips: add Octeon LWUX instruction target/mips: add Octeon LHUX instruction target/mips: add Octeon LBX instruction target/mips: split Octeon SEQI/SNEI decode target/mips: split Octeon SEQ/SNE decode target/mips: drop Octeon zero-register fast paths target/mips: fix Octeon arithmetic destination handling ... Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>