target/riscv: Use the tb->cs_base as the extend tb flags
We have more than 32-bits worth of state per TB, so use the tb->cs_base, which is otherwise unused for RISC-V, as the extend flag. Reviewed-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com> Reviewed-by: Chao Liu <chao.liu.zevorn@gmail.com> Signed-off-by: Max Chou <max.chou@sifive.com> Message-ID: <20260402125234.1371897-6-max.chou@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Max Chou committed
Apr 2, 2026 at 20:52 UTC
1c88ab9e77bdddc87a3ea0f1f2d3c1e0cd787e76
3 files changed
+10
-1
include/exec/translation-block.h
+1
@@ -65,6 +65,7 @@ struct TranslationBlock {
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* arm: an extension of tb->flags,
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* s390x: instruction data for EXECUTE,
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* sparc: the next pc of the instruction queue (for delay slots).
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+ * riscv: an extension of tb->flags,
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*/
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uint64_t cs_base;
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target/riscv/cpu.h
+3
@@ -703,6 +703,9 @@ FIELD(TB_FLAGS, BCFI_ENABLED, 28, 1)
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FIELD(TB_FLAGS, PM_PMM, 29, 2)
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FIELD(TB_FLAGS, PM_SIGNEXTEND, 31, 1)
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+FIELD(EXT_TB_FLAGS, MISA_EXT, 0, 32)
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+FIELD(EXT_TB_FLAGS, ALTFMT, 32, 1)
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+
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#ifdef TARGET_RISCV32
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#define riscv_cpu_mxl(env) ((void)(env), MXL_RV32)
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#else
target/riscv/tcg/tcg-cpu.c
+6
-1
@@ -104,6 +104,7 @@ static TCGTBCPUState riscv_get_tb_cpu_state(CPUState *cs)
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RISCVCPU *cpu = env_archcpu(env);
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RISCVExtStatus fs, vs;
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uint32_t flags = 0;
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+ uint64_t ext_flags = 0;
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bool pm_signext = riscv_cpu_virt_mem_enabled(env);
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if (cpu->cfg.ext_zve32x) {
@@ -118,6 +119,7 @@ static TCGTBCPUState riscv_get_tb_cpu_state(CPUState *cs)
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/* lmul encoded as in DisasContext::lmul */
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int8_t lmul = sextract32(FIELD_EX64(env->vtype, VTYPE, VLMUL), 0, 3);
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+ uint8_t altfmt = FIELD_EX64(env->vtype, VTYPE, ALTFMT);
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uint32_t vsew = FIELD_EX64(env->vtype, VTYPE, VSEW);
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uint32_t vlmax = vext_get_vlmax(cpu->cfg.vlenb, vsew, lmul);
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uint32_t maxsz = vlmax << vsew;
@@ -133,6 +135,7 @@ static TCGTBCPUState riscv_get_tb_cpu_state(CPUState *cs)
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flags = FIELD_DP32(flags, TB_FLAGS, VMA,
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FIELD_EX64(env->vtype, VTYPE, VMA));
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flags = FIELD_DP32(flags, TB_FLAGS, VSTART_EQ_ZERO, env->vstart == 0);
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+ ext_flags = FIELD_DP64(ext_flags, EXT_TB_FLAGS, ALTFMT, altfmt);
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} else {
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flags = FIELD_DP32(flags, TB_FLAGS, VILL, 1);
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}
@@ -189,10 +192,12 @@ static TCGTBCPUState riscv_get_tb_cpu_state(CPUState *cs)
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flags = FIELD_DP32(flags, TB_FLAGS, PM_PMM, riscv_pm_get_pmm(env));
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flags = FIELD_DP32(flags, TB_FLAGS, PM_SIGNEXTEND, pm_signext);
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+ ext_flags = FIELD_DP64(ext_flags, EXT_TB_FLAGS, MISA_EXT, env->misa_ext);
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+
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return (TCGTBCPUState){
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.pc = env->xl == MXL_RV32 ? env->pc & UINT32_MAX : env->pc,
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.flags = flags,
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- .cs_base = env->misa_ext,
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+ .cs_base = ext_flags,
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};
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}
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