hw/arm/fsl-imx8mm: Add GPIO controllers
Enabled GPIO controller emulation Also updated the GPIO IRQ lines of iMX8MM Reviewed-by: Philippe Mathieu-Daude <philmd@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Bernhard Beschow <shentey@gmail.com> Signed-off-by: Gaurav Sharma <gaurav.sharma_7@nxp.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Gaurav Sharma committed
Apr 21, 2026 at 12:22 UTC
1fc0cb911cfbafc9b370a7da7d09cc9039500eff
2 files changed
+68
hw/arm/fsl-imx8mm.c
+54
@@ -180,6 +180,11 @@ static void fsl_imx8mm_init(Object *obj)
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object_initialize_child(obj, name, &s->uart[i], TYPE_IMX_SERIAL);
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}
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+ for (i = 0; i < FSL_IMX8MM_NUM_GPIOS; i++) {
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+ g_autofree char *name = g_strdup_printf("gpio%d", i + 1);
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+ object_initialize_child(obj, name, &s->gpio[i], TYPE_IMX_GPIO);
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+ }
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+
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for (i = 0; i < FSL_IMX8MM_NUM_USDHCS; i++) {
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g_autofree char *name = g_strdup_printf("usdhc%d", i + 1);
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object_initialize_child(obj, name, &s->usdhc[i], TYPE_IMX_USDHC);
@@ -365,6 +370,54 @@ static void fsl_imx8mm_realize(DeviceState *dev, Error **errp)
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fsl_imx8mm_memmap[FSL_IMX8MM_OCRAM].addr,
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&s->ocram);
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+ /* GPIOs */
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+ for (i = 0; i < FSL_IMX8MM_NUM_GPIOS; i++) {
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+ static const struct {
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+ hwaddr addr;
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+ unsigned int irq_low;
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+ unsigned int irq_high;
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+ } gpio_table[FSL_IMX8MM_NUM_GPIOS] = {
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+ {
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+ fsl_imx8mm_memmap[FSL_IMX8MM_GPIO1].addr,
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+ FSL_IMX8MM_GPIO1_LOW_IRQ,
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+ FSL_IMX8MM_GPIO1_HIGH_IRQ
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+ },
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+ {
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+ fsl_imx8mm_memmap[FSL_IMX8MM_GPIO2].addr,
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+ FSL_IMX8MM_GPIO2_LOW_IRQ,
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+ FSL_IMX8MM_GPIO2_HIGH_IRQ
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+ },
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+ {
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+ fsl_imx8mm_memmap[FSL_IMX8MM_GPIO3].addr,
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+ FSL_IMX8MM_GPIO3_LOW_IRQ,
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+ FSL_IMX8MM_GPIO3_HIGH_IRQ
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+ },
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+ {
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+ fsl_imx8mm_memmap[FSL_IMX8MM_GPIO4].addr,
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+ FSL_IMX8MM_GPIO4_LOW_IRQ,
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+ FSL_IMX8MM_GPIO4_HIGH_IRQ
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+ },
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+ {
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+ fsl_imx8mm_memmap[FSL_IMX8MM_GPIO5].addr,
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+ FSL_IMX8MM_GPIO5_LOW_IRQ,
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+ FSL_IMX8MM_GPIO5_HIGH_IRQ
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+ },
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+ };
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+ object_property_set_bool(OBJECT(&s->gpio[i]), "has-edge-sel", true,
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+ &error_abort);
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+ object_property_set_bool(OBJECT(&s->gpio[i]), "has-upper-pin-irq",
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+ true, &error_abort);
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+ if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio[i]), errp)) {
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+ return;
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+ }
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+
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+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio[i]), 0, gpio_table[i].addr);
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+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 0,
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+ qdev_get_gpio_in(gicdev, gpio_table[i].irq_low));
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+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 1,
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+ qdev_get_gpio_in(gicdev, gpio_table[i].irq_high));
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+ }
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+
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/* USDHCs */
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for (i = 0; i < FSL_IMX8MM_NUM_USDHCS; i++) {
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static const struct {
@@ -423,6 +476,7 @@ static void fsl_imx8mm_realize(DeviceState *dev, Error **errp)
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case FSL_IMX8MM_CCM:
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case FSL_IMX8MM_GIC_DIST:
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case FSL_IMX8MM_GIC_REDIST:
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+ case FSL_IMX8MM_GPIO1 ... FSL_IMX8MM_GPIO5:
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case FSL_IMX8MM_PCIE1:
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case FSL_IMX8MM_PCIE_PHY1:
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case FSL_IMX8MM_RAM:
include/hw/arm/fsl-imx8mm.h
+14
@@ -12,6 +12,7 @@
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#include "cpu.h"
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#include "hw/char/imx_serial.h"
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+#include "hw/gpio/imx_gpio.h"
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#include "hw/intc/arm_gicv3_common.h"
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#include "hw/misc/imx7_snvs.h"
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#include "hw/misc/imx8mp_analog.h"
@@ -30,6 +31,7 @@ OBJECT_DECLARE_SIMPLE_TYPE(FslImx8mmState, FSL_IMX8MM)
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enum FslImx8mmConfiguration {
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FSL_IMX8MM_NUM_CPUS = 4,
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+ FSL_IMX8MM_NUM_GPIOS = 5,
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FSL_IMX8MM_NUM_IRQS = 128,
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FSL_IMX8MM_NUM_UARTS = 4,
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FSL_IMX8MM_NUM_USDHCS = 3,
@@ -40,6 +42,7 @@ struct FslImx8mmState {
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ARMCPU cpu[FSL_IMX8MM_NUM_CPUS];
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GICv3State gic;
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+ IMXGPIOState gpio[FSL_IMX8MM_NUM_GPIOS];
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IMX8MPCCMState ccm;
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IMX8MPAnalogState analog;
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IMX7SNVSState snvs;
@@ -171,6 +174,17 @@ enum FslImx8mmIrqs {
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FSL_IMX8MM_UART3_IRQ = 28,
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FSL_IMX8MM_UART4_IRQ = 29,
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+ FSL_IMX8MM_GPIO1_LOW_IRQ = 64,
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+ FSL_IMX8MM_GPIO1_HIGH_IRQ = 65,
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+ FSL_IMX8MM_GPIO2_LOW_IRQ = 66,
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+ FSL_IMX8MM_GPIO2_HIGH_IRQ = 67,
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+ FSL_IMX8MM_GPIO3_LOW_IRQ = 68,
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+ FSL_IMX8MM_GPIO3_HIGH_IRQ = 69,
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+ FSL_IMX8MM_GPIO4_LOW_IRQ = 70,
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+ FSL_IMX8MM_GPIO4_HIGH_IRQ = 71,
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+ FSL_IMX8MM_GPIO5_LOW_IRQ = 72,
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+ FSL_IMX8MM_GPIO5_HIGH_IRQ = 73,
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+
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FSL_IMX8MM_PCI_INTA_IRQ = 122,
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FSL_IMX8MM_PCI_INTB_IRQ = 123,
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FSL_IMX8MM_PCI_INTC_IRQ = 124,