hw/intc/arm_gicv5: Implement CoreSight ID registers
The GICv5 register blocks all implement the usual Arm CoreSight ID registers; implement these for the IRS. Although we only have one callsite at the moment, the ITS config frame uses the same ID register values, so we abstract this out into a function we can reuse later. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20260327111700.795099-33-peter.maydell@linaro.org
Peter Maydell committed
Mar 27, 2026 at 11:16 UTC
22232793ecb8e842f4a310e5419f1cb90dc3fb4b
1 file changed
+35
hw/intc/arm_gicv5.c
+35
@@ -285,6 +285,9 @@ REG64(IRS_SWERR_SYNDROMER0, 0x3c8)
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REG64(IRS_SWERR_SYNDROMER1, 0x3d0)
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FIELD(IRS_SWERR_SYNDROMER2, ADDR, 3, 53)
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+REG32(IRS_IDREGS, 0xffd0)
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+REG32(IRS_DEVARCH, 0xffbc)
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+
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FIELD(L1_ISTE, VALID, 0, 1)
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FIELD(L1_ISTE, L2_ADDR, 12, 44)
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@@ -310,6 +313,31 @@ FIELD(ICSR, HM, 5, 1)
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FIELD(ICSR, PRIORITY, 11, 5)
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FIELD(ICSR, IAFFID, 32, 16)
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+#define IRS_DEVARCH_VALUE ((0x23b << 31) | (0x1 << 20) | 0x5a19)
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+
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+static uint32_t gicv5_idreg(int regoffset)
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+{
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+ /*
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+ * As with the main IRS_IIDR, we don't identify as a specific
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+ * hardware GICv5 implementation. Arm suggests that the
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+ * Implementer, Product, etc in IRS_IIDR should also be reported
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+ * here, so we do that.
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+ */
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+ static const uint8_t gic_ids[] = {
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+ QEMU_GICV5_IMPLEMENTER >> 8, 0x00, 0x00, 0x00, /* PIDR4..PIDR7 */
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+ QEMU_GICV5_PRODUCTID & 0xff, /* PIDR0 */
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+ ((QEMU_GICV5_PRODUCTID >> 8) |
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+ ((QEMU_GICV5_IMPLEMENTER & 0xf) << 4)), /* PIDR1 */
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+ ((QEMU_GICV5_REVISION << 4) | (1 << 3) |
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+ ((QEMU_GICV5_IMPLEMENTER & 0x70) >> 4)), /* PIDR2 */
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+ QEMU_GICV5_VARIANT << 4, /* PIDR3 */
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+ 0x0D, 0xF0, 0x05, 0xB1, /* CIDR0..CIDR3 */
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+ };
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+
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+ regoffset /= 4;
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+ return gic_ids[regoffset];
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+}
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+
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static GICv5SPIState *spi_for_selr(GICv5Common *cs, GICv5Domain domain)
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{
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/*
@@ -1124,6 +1152,13 @@ static bool config_readl(GICv5 *s, GICv5Domain domain, hwaddr offset,
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}
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*data = v;
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return true;
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+ case A_IRS_DEVARCH:
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+ *data = IRS_DEVARCH_VALUE;
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+ return true;
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+ case A_IRS_IDREGS ... A_IRS_IDREGS + 0x2f:
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+ /* CoreSight ID registers */
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+ *data = gicv5_idreg(offset - A_IRS_IDREGS);
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+ return true;
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}
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return false;