target/riscv/tcg: use isa_edata_arr[] to enable max exts
Use isa_edata_arr[] to enable all feasible extensions. Filter experimental and vendor extensions by checking if the riscv,isa or the prop name starts with 'x'. Signed-off-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20260512032926.1978818-11-daniel.barboza@oss.qualcomm.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Daniel Henrique Barboza committed
May 12, 2026 at 00:29 UTC
225b8ee51facf0eb18ec5536771283aa46e8a6ab
1 file changed
+8
-3
target/riscv/tcg/tcg-cpu.c
+8
-3
@@ -1614,13 +1614,18 @@ static void riscv_init_max_cpu_extensions(Object *obj)
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{
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RISCVCPU *cpu = RISCV_CPU(obj);
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CPURISCVState *env = &cpu->env;
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- const RISCVCPUMultiExtConfig *prop;
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+ const RISCVIsaExtData *edata;
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/* Enable RVG and RVV that are disabled by default */
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riscv_cpu_set_misa_ext(env, env->misa_ext | RVB | RVG | RVV);
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- for (prop = riscv_cpu_extensions; prop && prop->name; prop++) {
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- isa_ext_update_enabled(cpu, prop->offset, true);
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+ for (edata = isa_edata_arr; edata && edata->name; edata++) {
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+ if (edata->name[0] == 'x'
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+ || (edata->prop_name && edata->prop_name[0] == 'x')) {
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+ continue;
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+ }
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+
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+ isa_ext_update_enabled(cpu, edata->ext_enable_offset, true);
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}
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/*