target/arm: GICv5 cpuif: Implement ICC_PCR_EL1
Implement the ICC_PCR_* registers. These hold the physical priority mask for each interrupt domain -- an HPPI is only sufficiently high priority to preempt if it is higher priority than this mask value. Here we just implement the access to this data. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com> Message-id: 20260327111700.795099-46-peter.maydell@linaro.org
Peter Maydell committed
Mar 27, 2026 at 11:16 UTC
23ed9a8c7690820f619b62cf9588b2d269bc9d23
2 files changed
+32
target/arm/cpu.h
+1
@@ -605,6 +605,7 @@ typedef struct CPUArchState {
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uint64_t icc_icsr_el1;
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uint64_t icc_apr[NUM_GICV5_DOMAINS];
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uint64_t icc_cr0[NUM_GICV5_DOMAINS];
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+ uint64_t icc_pcr[NUM_GICV5_DOMAINS];
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/* Most PPI registers have 1 bit per PPI, so 64 PPIs to a register */
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uint64_t ppi_active[GICV5_NUM_PPIS / 64];
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uint64_t ppi_hm[GICV5_NUM_PPIS / 64];
target/arm/tcg/gicv5-cpuif.c
+31
@@ -49,6 +49,8 @@ FIELD(ICC_CR0, LINK_IDLE, 2, 1)
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FIELD(ICC_CR0, IPPT, 32, 6)
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FIELD(ICC_CR0, PID, 38, 1)
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+FIELD(ICC_PCR, PRIORITY, 0, 5)
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+
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/*
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* We implement 24 bits of interrupt ID, the mandated 5 bits of priority,
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* and no legacy GICv3.3 vcpu interface (yet)
@@ -383,6 +385,28 @@ static void gic_icc_cr0_el1_reset(CPUARMState *env, const ARMCPRegInfo *ri)
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}
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}
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+static uint64_t gic_icc_pcr_el1_read(CPUARMState *env, const ARMCPRegInfo *ri)
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+{
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+ GICv5Domain domain = gicv5_logical_domain(env);
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+ return env->gicv5_cpuif.icc_pcr[domain];
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+}
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+
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+static void gic_icc_pcr_el1_write(CPUARMState *env, const ARMCPRegInfo *ri,
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+ uint64_t value)
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+{
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+ GICv5Domain domain = gicv5_logical_domain(env);
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+
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+ value &= R_ICC_PCR_PRIORITY_MASK;
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+ env->gicv5_cpuif.icc_pcr[domain] = value;
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+}
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+
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+static void gic_icc_pcr_el1_reset(CPUARMState *env, const ARMCPRegInfo *ri)
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+{
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+ for (int i = 0; i < ARRAY_SIZE(env->gicv5_cpuif.icc_pcr); i++) {
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+ env->gicv5_cpuif.icc_pcr[i] = 0;
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+ }
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+}
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+
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static const ARMCPRegInfo gicv5_cpuif_reginfo[] = {
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/*
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* Barrier: wait until the effects of a cpuif system register
@@ -548,6 +572,13 @@ static const ARMCPRegInfo gicv5_cpuif_reginfo[] = {
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.writefn = gic_icc_cr0_el1_write,
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.resetfn = gic_icc_cr0_el1_reset,
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},
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+ { .name = "ICC_PCR_EL1", .state = ARM_CP_STATE_AA64,
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+ .opc0 = 3, .opc1 = 1, .crn = 12, .crm = 0, .opc2 = 2,
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+ .access = PL1_RW, .type = ARM_CP_IO | ARM_CP_NO_RAW,
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+ .readfn = gic_icc_pcr_el1_read,
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+ .writefn = gic_icc_pcr_el1_write,
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+ .resetfn = gic_icc_pcr_el1_reset,
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+ },
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{ .name = "ICC_HAPR_EL1", .state = ARM_CP_STATE_AA64,
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.opc0 = 3, .opc1 = 1, .crn = 12, .crm = 0, .opc2 = 3,
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.access = PL1_R, .type = ARM_CP_IO | ARM_CP_NO_RAW,