target/riscv: Initialize riscv_excp_names[] and riscv_intr_names[] using designated initializer
Use designated initializers to initialize riscv_excp_names[] and riscv_intr_names[] so that we don't have to explicitly add "reserved" items. Also, add the missing trap names: sw_check, hw_error, virt_illegal_instruction, semihost, s_guest_external, and counter_overflow. Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Max Chou <max.chou@sifive.com> Reviewed-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com> Reviewed-by: Nutty Liu <nutty.liu@hotmail.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20260421071107.2848439-1-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Frank Chang committed
Apr 21, 2026 at 15:11 UTC
23fe1e581311d9eaba12621c7eec25d631b5560e
1 file changed
+45
-44
target/riscv/cpu.c
+45
-44
@@ -328,60 +328,61 @@ const char * const riscv_rvv_regnames[] = {
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};
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static const char * const riscv_excp_names[] = {
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- "misaligned_fetch",
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- "fault_fetch",
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- "illegal_instruction",
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- "breakpoint",
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- "misaligned_load",
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- "fault_load",
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- "misaligned_store",
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- "fault_store",
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- "user_ecall",
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- "supervisor_ecall",
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- "hypervisor_ecall",
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- "machine_ecall",
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- "exec_page_fault",
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- "load_page_fault",
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- "reserved",
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- "store_page_fault",
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- "double_trap",
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- "reserved",
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- "reserved",
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- "reserved",
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- "guest_exec_page_fault",
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- "guest_load_page_fault",
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- "reserved",
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- "guest_store_page_fault",
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+ [RISCV_EXCP_INST_ADDR_MIS] = "misaligned_fetch",
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+ [RISCV_EXCP_INST_ACCESS_FAULT] = "fault_fetch",
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+ [RISCV_EXCP_ILLEGAL_INST] = "illegal_instruction",
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+ [RISCV_EXCP_BREAKPOINT] = "breakpoint",
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+ [RISCV_EXCP_LOAD_ADDR_MIS] = "misaligned_load",
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+ [RISCV_EXCP_LOAD_ACCESS_FAULT] = "fault_load",
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+ [RISCV_EXCP_STORE_AMO_ADDR_MIS] = "misaligned_store",
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+ [RISCV_EXCP_STORE_AMO_ACCESS_FAULT] = "fault_store",
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+ [RISCV_EXCP_U_ECALL] = "user_ecall",
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+ [RISCV_EXCP_S_ECALL] = "supervisor_ecall",
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+ [RISCV_EXCP_VS_ECALL] = "hypervisor_ecall",
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+ [RISCV_EXCP_M_ECALL] = "machine_ecall",
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+ [RISCV_EXCP_INST_PAGE_FAULT] = "exec_page_fault",
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+ [RISCV_EXCP_LOAD_PAGE_FAULT] = "load_page_fault",
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+ [RISCV_EXCP_STORE_PAGE_FAULT] = "store_page_fault",
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+ [RISCV_EXCP_DOUBLE_TRAP] = "double_trap",
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+ [RISCV_EXCP_SW_CHECK] = "sw_check",
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+ [RISCV_EXCP_HW_ERR] = "hw_error",
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+ [RISCV_EXCP_INST_GUEST_PAGE_FAULT] = "guest_exec_page_fault",
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+ [RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT] = "guest_load_page_fault",
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+ [RISCV_EXCP_VIRT_INSTRUCTION_FAULT] = "virt_illegal_instruction",
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+ [RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT] = "guest_store_page_fault",
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+ [RISCV_EXCP_SEMIHOST] = "semihost",
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};
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static const char * const riscv_intr_names[] = {
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- "u_software",
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- "s_software",
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- "vs_software",
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- "m_software",
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- "u_timer",
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- "s_timer",
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- "vs_timer",
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- "m_timer",
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- "u_external",
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- "s_external",
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- "vs_external",
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- "m_external",
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- "reserved",
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- "reserved",
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- "reserved",
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- "reserved"
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+ [IRQ_U_SOFT] = "u_software",
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+ [IRQ_S_SOFT] = "s_software",
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+ [IRQ_VS_SOFT] = "vs_software",
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+ [IRQ_M_SOFT] = "m_software",
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+ [IRQ_U_TIMER] = "u_timer",
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+ [IRQ_S_TIMER] = "s_timer",
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+ [IRQ_VS_TIMER] = "vs_timer",
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+ [IRQ_M_TIMER] = "m_timer",
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+ [IRQ_U_EXT] = "u_external",
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+ [IRQ_S_EXT] = "s_external",
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+ [IRQ_VS_EXT] = "vs_external",
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+ [IRQ_M_EXT] = "m_external",
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+ [IRQ_S_GEXT] = "s_guest_external",
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+ [IRQ_PMU_OVF] = "counter_overflow",
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};
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const char *riscv_cpu_get_trap_name(target_ulong cause, bool async)
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{
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if (async) {
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- return (cause < ARRAY_SIZE(riscv_intr_names)) ?
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- riscv_intr_names[cause] : "(unknown)";
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+ if ((cause < ARRAY_SIZE(riscv_intr_names)) && riscv_intr_names[cause]) {
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+ return riscv_intr_names[cause];
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+ }
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} else {
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- return (cause < ARRAY_SIZE(riscv_excp_names)) ?
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- riscv_excp_names[cause] : "(unknown)";
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+ if ((cause < ARRAY_SIZE(riscv_excp_names)) && riscv_excp_names[cause]) {
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+ return riscv_excp_names[cause];
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+ }
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}
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+
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+ return "(unknown)";
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}
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void riscv_cpu_set_misa_ext(CPURISCVState *env, uint32_t ext)