@samitouri / QOSamiQemu / commits / 24037a7046

target/arm: GICv5 cpuif: Implement ICC_CR0_EL1

Implement ICC_CR0_EL1, which is the main control register. This is banked between interrupt domains in the same way as ICC_APR_*. The GICv5 spec assumes that typically there will need to be a hardware handshake between the CPU and the IRS, which is kicked off by guest software setting a LINK bit in this register to bring the link between the two online. However it is permitted to have an implementation where the link is permanently up. We take advantage of this, so our LINK and LINK_IDLE bits are read-only and always 1. This means the only interesting bit in this register for us is the main enable bit: when disabled for a domain, the cpuif considers that there is never an available highest priority interrupt. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com> Message-id: 20260327111700.795099-45-peter.maydell@linaro.org

Peter Maydell committed Mar 27, 2026 at 11:16 UTC 24037a7046d2b38eec62eb67fd88acf9bb73865e
2 files changed +45
target/arm/cpu.h
+1
@@ -604,6 +604,7 @@ typedef struct CPUArchState {
604 /* GICv5 CPU interface data */
605 uint64_t icc_icsr_el1;
606 uint64_t icc_apr[NUM_GICV5_DOMAINS];
607 + uint64_t icc_cr0[NUM_GICV5_DOMAINS];
608 /* Most PPI registers have 1 bit per PPI, so 64 PPIs to a register */
609 uint64_t ppi_active[GICV5_NUM_PPIS / 64];
610 uint64_t ppi_hm[GICV5_NUM_PPIS / 64];
target/arm/tcg/gicv5-cpuif.c
+44
@@ -43,6 +43,12 @@ FIELD(ICC_IDR0_EL1, ID_BITS, 0, 4)
43 FIELD(ICC_IDR0_EL1, PRI_BITS, 4, 4)
44 FIELD(ICC_IDR0_EL1, GCIE_LEGACY, 8, 4)
45
46 +FIELD(ICC_CR0, EN, 0, 1)
47 +FIELD(ICC_CR0, LINK, 1, 1)
48 +FIELD(ICC_CR0, LINK_IDLE, 2, 1)
49 +FIELD(ICC_CR0, IPPT, 32, 6)
50 +FIELD(ICC_CR0, PID, 38, 1)
51 +
52 /*
53 * We implement 24 bits of interrupt ID, the mandated 5 bits of priority,
54 * and no legacy GICv3.3 vcpu interface (yet)
@@ -346,6 +352,37 @@ static uint64_t gic_icc_hapr_el1_read(CPUARMState *env, const ARMCPRegInfo *ri)
352 return gic_running_prio(env, gicv5_current_phys_domain(env));
353 }
354
355 +/* ICC_CR0_EL1 is also banked */
356 +static uint64_t gic_icc_cr0_el1_read(CPUARMState *env, const ARMCPRegInfo *ri)
357 +{
358 + GICv5Domain domain = gicv5_logical_domain(env);
359 + return env->gicv5_cpuif.icc_cr0[domain];
360 +}
361 +
362 +static void gic_icc_cr0_el1_write(CPUARMState *env, const ARMCPRegInfo *ri,
363 + uint64_t value)
364 +{
365 + /*
366 + * For our implementation the link to the IRI is always connected,
367 + * so LINK and LINK_IDLE are always 1. Without EL3, PID and IPPT
368 + * are RAZ/WI, so the only writeable bit is the main enable bit EN.
369 + */
370 + GICv5Domain domain = gicv5_logical_domain(env);
371 + value &= R_ICC_CR0_EN_MASK;
372 + value |= R_ICC_CR0_LINK_MASK | R_ICC_CR0_LINK_IDLE_MASK;
373 +
374 + env->gicv5_cpuif.icc_cr0[domain] = value;
375 +}
376 +
377 +static void gic_icc_cr0_el1_reset(CPUARMState *env, const ARMCPRegInfo *ri)
378 +{
379 + /* The link is always connected so we reset with LINK and LINK_IDLE set */
380 + for (int i = 0; i < ARRAY_SIZE(env->gicv5_cpuif.icc_cr0); i++) {
381 + env->gicv5_cpuif.icc_cr0[i] =
382 + R_ICC_CR0_LINK_MASK | R_ICC_CR0_LINK_IDLE_MASK;
383 + }
384 +}
385 +
386 static const ARMCPRegInfo gicv5_cpuif_reginfo[] = {
387 /*
388 * Barrier: wait until the effects of a cpuif system register
@@ -504,6 +541,13 @@ static const ARMCPRegInfo gicv5_cpuif_reginfo[] = {
541 .writefn = gic_icc_apr_el1_write,
542 .resetfn = gic_icc_apr_el1_reset,
543 },
544 + { .name = "ICC_CR0_EL1", .state = ARM_CP_STATE_AA64,
545 + .opc0 = 3, .opc1 = 1, .crn = 12, .crm = 0, .opc2 = 1,
546 + .access = PL1_RW, .type = ARM_CP_IO | ARM_CP_NO_RAW,
547 + .readfn = gic_icc_cr0_el1_read,
548 + .writefn = gic_icc_cr0_el1_write,
549 + .resetfn = gic_icc_cr0_el1_reset,
550 + },
551 { .name = "ICC_HAPR_EL1", .state = ARM_CP_STATE_AA64,
552 .opc0 = 3, .opc1 = 1, .crn = 12, .crm = 0, .opc2 = 3,
553 .access = PL1_R, .type = ARM_CP_IO | ARM_CP_NO_RAW,