target/riscv: rvv: Allow fractional LMUL on vector SHA instructions

Vector SHA instructions incorrectly raise an illegal instruction exception when LMUL < 1. The ISA only states that LMUL*VLEN >= EGW: For element-group instructions, LMUL*VLEN must always be at least as large as EGW, otherwise an illegal-instruction exception is raised, even if vl=0. There is already a check for this: MAXSZ(s) >= egw_bytes so just remove the check for a fractional LMUL. Signed-off-by: Anton Blanchard <antonb@tenstorrent.com> Reviewed-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com> Message-ID: <20260104233724.192886-1-antonb@tenstorrent.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>