hw/arm/fsl-imx8mm: Adding support for Watchdog Timers
It enables emulation of WDT in iMX8MM Added WDT IRQ lines Reviewed-by: Philippe Mathieu-Daude <philmd@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Bernhard Beschow <shentey@gmail.com> Signed-off-by: Gaurav Sharma <gaurav.sharma_7@nxp.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Gaurav Sharma committed
Apr 21, 2026 at 12:22 UTC
2b8b30578cea9d24896df7709140c7a900e45ca1
3 files changed
+36
hw/arm/Kconfig
+1
@@ -629,6 +629,7 @@ config FSL_IMX8MM
629
select SDHCI
630
select PCI_EXPRESS_DESIGNWARE
631
select PCI_EXPRESS_FSL_IMX8M_PHY
632
+ select WDT_IMX2
633
634
config FSL_IMX8MM_EVK
635
bool
hw/arm/fsl-imx8mm.c
+28
@@ -200,6 +200,11 @@ static void fsl_imx8mm_init(Object *obj)
200
object_initialize_child(obj, name, &s->spi[i], TYPE_IMX_SPI);
201
}
202
203
+ for (i = 0; i < FSL_IMX8MM_NUM_WDTS; i++) {
204
+ g_autofree char *name = g_strdup_printf("wdt%d", i);
205
+ object_initialize_child(obj, name, &s->wdt[i], TYPE_IMX2_WDT);
206
+ }
207
+
208
object_initialize_child(obj, "pcie", &s->pcie, TYPE_DESIGNWARE_PCIE_HOST);
209
object_initialize_child(obj, "pcie_phy", &s->pcie_phy,
210
TYPE_FSL_IMX8M_PCIE_PHY);
@@ -496,6 +501,28 @@ static void fsl_imx8mm_realize(DeviceState *dev, Error **errp)
501
sysbus_mmio_map(SYS_BUS_DEVICE(&s->snvs), 0,
502
fsl_imx8mm_memmap[FSL_IMX8MM_SNVS_HP].addr);
503
504
+ /* Watchdogs */
505
+ for (i = 0; i < FSL_IMX8MM_NUM_WDTS; i++) {
506
+ static const struct {
507
+ hwaddr addr;
508
+ unsigned int irq;
509
+ } wdog_table[FSL_IMX8MM_NUM_WDTS] = {
510
+ { fsl_imx8mm_memmap[FSL_IMX8MM_WDOG1].addr, FSL_IMX8MM_WDOG1_IRQ },
511
+ { fsl_imx8mm_memmap[FSL_IMX8MM_WDOG2].addr, FSL_IMX8MM_WDOG2_IRQ },
512
+ { fsl_imx8mm_memmap[FSL_IMX8MM_WDOG3].addr, FSL_IMX8MM_WDOG3_IRQ },
513
+ };
514
+
515
+ object_property_set_bool(OBJECT(&s->wdt[i]), "pretimeout-support",
516
+ true, &error_abort);
517
+ if (!sysbus_realize(SYS_BUS_DEVICE(&s->wdt[i]), errp)) {
518
+ return;
519
+ }
520
+
521
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt[i]), 0, wdog_table[i].addr);
522
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->wdt[i]), 0,
523
+ qdev_get_gpio_in(gicdev, wdog_table[i].irq));
524
+ }
525
+
526
/* PCIe */
527
if (!sysbus_realize(SYS_BUS_DEVICE(&s->pcie), errp)) {
528
return;
@@ -537,6 +564,7 @@ static void fsl_imx8mm_realize(DeviceState *dev, Error **errp)
564
case FSL_IMX8MM_SNVS_HP:
565
case FSL_IMX8MM_UART1 ... FSL_IMX8MM_UART4:
566
case FSL_IMX8MM_USDHC1 ... FSL_IMX8MM_USDHC3:
567
+ case FSL_IMX8MM_WDOG1 ... FSL_IMX8MM_WDOG3:
568
/* device implemented and treated above */
569
break;
570
include/hw/arm/fsl-imx8mm.h
+7
@@ -22,6 +22,7 @@
22
#include "hw/pci-host/fsl_imx8m_phy.h"
23
#include "hw/sd/sdhci.h"
24
#include "hw/ssi/imx_spi.h"
25
+#include "hw/watchdog/wdt_imx2.h"
26
#include "qom/object.h"
27
#include "qemu/units.h"
28
@@ -39,6 +40,7 @@ enum FslImx8mmConfiguration {
40
FSL_IMX8MM_NUM_IRQS = 128,
41
FSL_IMX8MM_NUM_UARTS = 4,
42
FSL_IMX8MM_NUM_USDHCS = 3,
43
+ FSL_IMX8MM_NUM_WDTS = 3,
44
};
45
46
struct FslImx8mmState {
@@ -55,6 +57,7 @@ struct FslImx8mmState {
57
IMXSerialState uart[FSL_IMX8MM_NUM_UARTS];
58
MemoryRegion ocram;
59
SDHCIState usdhc[FSL_IMX8MM_NUM_USDHCS];
60
+ IMX2WdtState wdt[FSL_IMX8MM_NUM_WDTS];
61
DesignwarePCIEHost pcie;
62
FslImx8mPciePhyState pcie_phy;
63
};
@@ -200,6 +203,10 @@ enum FslImx8mmIrqs {
203
FSL_IMX8MM_GPIO5_LOW_IRQ = 72,
204
FSL_IMX8MM_GPIO5_HIGH_IRQ = 73,
205
206
+ FSL_IMX8MM_WDOG1_IRQ = 78,
207
+ FSL_IMX8MM_WDOG2_IRQ = 79,
208
+ FSL_IMX8MM_WDOG3_IRQ = 10,
209
+
210
FSL_IMX8MM_PCI_INTA_IRQ = 122,
211
FSL_IMX8MM_PCI_INTB_IRQ = 123,
212
FSL_IMX8MM_PCI_INTC_IRQ = 124,