target/arm: GICv5 cpuif: Implement PPI enable register
Implement the GICv5 register which holds the enable state of PPIs: ICC_PPI_ENABLER<n>_EL1. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com> Message-id: 20260327111700.795099-40-peter.maydell@linaro.org
Peter Maydell committed
Mar 27, 2026 at 11:16 UTC
2f36257492dcd66438f2f00560b37fd9044ef00a
2 files changed
+19
target/arm/cpu.h
+1
@@ -606,6 +606,7 @@ typedef struct CPUArchState {
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uint64_t ppi_active[GICV5_NUM_PPIS / 64];
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uint64_t ppi_hm[GICV5_NUM_PPIS / 64];
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uint64_t ppi_pend[GICV5_NUM_PPIS / 64];
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+ uint64_t ppi_enable[GICV5_NUM_PPIS / 64];
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} gicv5_cpuif;
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struct {
target/arm/tcg/gicv5-cpuif.c
+18
@@ -219,6 +219,12 @@ static void gic_ppi_spend_write(CPUARMState *env, const ARMCPRegInfo *ri,
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raw_write(env, ri, old | value);
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}
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+static void gic_ppi_enable_write(CPUARMState *env, const ARMCPRegInfo *ri,
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+ uint64_t value)
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+{
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+ raw_write(env, ri, value);
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+}
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+
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static const ARMCPRegInfo gicv5_cpuif_reginfo[] = {
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/*
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* Barrier: wait until the effects of a cpuif system register
@@ -334,6 +340,18 @@ static const ARMCPRegInfo gicv5_cpuif_reginfo[] = {
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.fieldoffset = offsetof(CPUARMState, gicv5_cpuif.ppi_hm[1]),
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.resetvalue = PPI_HMR1_RESET,
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},
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+ { .name = "ICC_PPI_ENABLER0_EL1", .state = ARM_CP_STATE_AA64,
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+ .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 10, .opc2 = 6,
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+ .access = PL1_RW, .type = ARM_CP_IO | ARM_CP_NO_RAW,
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+ .fieldoffset = offsetof(CPUARMState, gicv5_cpuif.ppi_enable[0]),
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+ .writefn = gic_ppi_enable_write,
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+ },
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+ { .name = "ICC_PPI_ENABLER1_EL1", .state = ARM_CP_STATE_AA64,
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+ .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 10, .opc2 = 7,
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+ .access = PL1_RW, .type = ARM_CP_IO | ARM_CP_NO_RAW,
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+ .fieldoffset = offsetof(CPUARMState, gicv5_cpuif.ppi_enable[1]),
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+ .writefn = gic_ppi_enable_write,
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+ },
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{ .name = "ICC_PPI_CPENDR0_EL1", .state = ARM_CP_STATE_AA64,
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.opc0 = 3, .opc1 = 0, .crn = 12, .crm = 13, .opc2 = 4,
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.access = PL1_RW, .type = ARM_CP_ALIAS | ARM_CP_IO | ARM_CP_NO_RAW,