target/riscv: add draft RISC-V Zbr ext as xbr0p93
This extension was not ratified with the Zb[abcs] bitmanip extensions. This is the latest draft version (0.93) as implemented by the Ibex core. These instructions are in the reserved encoding space but have not been ratified and could conflict with future ratified instructions. For this reason they are added as a vendor extension to support Ibex's impl. Signed-off-by: James Wainwright <james.wainwright@lowrisc.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20260320134254.217123-3-james.wainwright@lowrisc.org> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Emmanuel Blot committed
Mar 20, 2026 at 13:42 UTC
32bbab666e08856c1a6660c3743a4493170a9afd
12 files changed
+178
-1
MAINTAINERS
+3
@@ -1729,6 +1729,9 @@ F: hw/riscv/opentitan.c
1729
F: hw/*/ibex_*.c
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F: include/hw/riscv/opentitan.h
1731
F: include/hw/*/ibex_*.h
1732
+F: target/riscv/insn_trans/trans_xthead.c.inc
1733
+F: target/riscv/xlrbr.decode
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+F: tests/tcg/riscv64/test-crc32.S
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1736
Microchip PolarFire SoC Icicle Kit
1737
L: qemu-riscv@nongnu.org
target/riscv/bitmanip_helper.c
+20
@@ -23,6 +23,8 @@
23
#include "exec/target_long.h"
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#include "exec/helper-proto.h"
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#include "tcg/tcg.h"
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+#include "qemu/crc32.h"
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+#include "qemu/crc32c.h"
28
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target_ulong HELPER(clmul)(target_ulong rs1, target_ulong rs2)
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{
@@ -129,3 +131,21 @@ target_ulong HELPER(xperm8)(target_ulong rs1, target_ulong rs2)
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{
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return do_xperm(rs1, rs2, 3);
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}
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+
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+target_ulong HELPER(crc32)(target_ulong rs1, target_ulong sz)
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+{
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+ for (target_ulong i = 0; i < sz; i++) {
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+ rs1 = crc32_table[rs1 & 0xFF] ^ (rs1 >> 8);
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+ }
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+
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+ return rs1;
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+}
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+
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+target_ulong HELPER(crc32c)(target_ulong rs1, target_ulong sz)
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+{
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+ for (target_ulong i = 0; i < sz; i++) {
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+ rs1 = crc32c_table[rs1 & 0xFF] ^ (rs1 >> 8);
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+ }
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+
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+ return rs1;
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+}
target/riscv/cpu.c
+3
-1
@@ -1373,6 +1373,7 @@ const RISCVCPUMultiExtConfig riscv_cpu_vendor_exts[] = {
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MULTI_EXT_CFG_BOOL("xmipscbop", ext_xmipscbop, false),
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MULTI_EXT_CFG_BOOL("xmipscmov", ext_xmipscmov, false),
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MULTI_EXT_CFG_BOOL("xmipslsp", ext_xmipslsp, false),
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+ MULTI_EXT_CFG_BOOL("xlrbr", ext_xlrbr, false),
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{ },
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};
@@ -3059,7 +3060,8 @@ static const TypeInfo riscv_cpu_type_infos[] = {
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.cfg.ext_zba = true,
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.cfg.ext_zbb = true,
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.cfg.ext_zbc = true,
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- .cfg.ext_zbs = true
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+ .cfg.ext_zbs = true,
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+ .cfg.ext_xlrbr = true
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),
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DEFINE_RISCV_CPU(TYPE_RISCV_CPU_SIFIVE_E31, TYPE_RISCV_CPU_SIFIVE_E,
target/riscv/cpu_cfg.h
+1
@@ -69,5 +69,6 @@ MATERIALISE_EXT_PREDICATE(xtheadmemidx)
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MATERIALISE_EXT_PREDICATE(xtheadmempair)
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MATERIALISE_EXT_PREDICATE(xtheadsync)
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MATERIALISE_EXT_PREDICATE(XVentanaCondOps)
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+MATERIALISE_EXT_PREDICATE(xlrbr);
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#endif
target/riscv/cpu_cfg_fields.h.inc
+1
@@ -154,6 +154,7 @@ BOOL_FIELD(ext_XVentanaCondOps)
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BOOL_FIELD(ext_xmipscbop)
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BOOL_FIELD(ext_xmipscmov)
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BOOL_FIELD(ext_xmipslsp)
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+BOOL_FIELD(ext_xlrbr)
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BOOL_FIELD(mmu)
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BOOL_FIELD(pmp)
target/riscv/helper.h
+2
@@ -84,6 +84,8 @@ DEF_HELPER_FLAGS_1(unzip, TCG_CALL_NO_RWG_SE, tl, tl)
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DEF_HELPER_FLAGS_1(zip, TCG_CALL_NO_RWG_SE, tl, tl)
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DEF_HELPER_FLAGS_2(xperm4, TCG_CALL_NO_RWG_SE, tl, tl, tl)
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DEF_HELPER_FLAGS_2(xperm8, TCG_CALL_NO_RWG_SE, tl, tl, tl)
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+DEF_HELPER_FLAGS_2(crc32, TCG_CALL_NO_RWG_SE, tl, tl, tl)
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+DEF_HELPER_FLAGS_2(crc32c, TCG_CALL_NO_RWG_SE, tl, tl, tl)
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/* Floating Point - Half Precision */
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DEF_HELPER_FLAGS_3(fadd_h, TCG_CALL_NO_RWG, i64, env, i64, i64)
target/riscv/insn_trans/trans_xlrbr.c.inc
new
+45
@@ -0,0 +1,45 @@
1
+/*
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+ * RISC-V translation routines for xlrbr matching the unratified Zbr CRC32
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+ * bitmanip extension v0.93.
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+ *
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+ * Copyright (c) 2026 Rivos Inc.
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+ *
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+ * SPDX-License-Identifier: GPL-2.0-or-later
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+ */
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+
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+#define REQUIRE_XLRBR(ctx) do { \
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+ if (!ctx->cfg_ptr->ext_xlrbr) { \
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+ return false; \
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+ } \
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+} while (0)
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+
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+static bool gen_crc(DisasContext *ctx, arg_r2 *a,
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+ void (*func)(TCGv, TCGv, TCGv), TCGv tsz)
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+{
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+ REQUIRE_XLRBR(ctx);
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+ TCGv dest = dest_gpr(ctx, a->rd);
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+ TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE);
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+
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+ func(dest, src1, tsz);
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+ gen_set_gpr(ctx, a->rd, dest);
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+
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+ return true;
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+}
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+
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+#define TRANS_CRC32(NAME, SIZE) \
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+ static bool trans_crc32_##NAME(DisasContext *ctx, arg_r2 *a) \
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+ { if (SIZE == 8) { REQUIRE_64BIT(ctx); }; \
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+ return gen_crc(ctx, a, gen_helper_crc32, tcg_constant_tl(SIZE)); }
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+#define TRANS_CRC32C(NAME, SIZE) \
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+ static bool trans_crc32c_##NAME(DisasContext *ctx, arg_r2 *a) \
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+ { if (SIZE == 8) { REQUIRE_64BIT(ctx); }; \
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+ return gen_crc(ctx, a, gen_helper_crc32c, tcg_constant_tl(SIZE)); }
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+
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+TRANS_CRC32(b, 1);
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+TRANS_CRC32(h, 2);
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+TRANS_CRC32(w, 4);
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+TRANS_CRC32(d, 8);
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+TRANS_CRC32C(b, 1);
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+TRANS_CRC32C(h, 2);
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+TRANS_CRC32C(w, 4);
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+TRANS_CRC32C(d, 8);
target/riscv/meson.build
+1
@@ -5,6 +5,7 @@ gen = [
5
decodetree.process('xthead.decode', extra_args: '--static-decode=decode_xthead'),
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decodetree.process('XVentanaCondOps.decode', extra_args: '--static-decode=decode_XVentanaCodeOps'),
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decodetree.process('xmips.decode', extra_args: '--static-decode=decode_xmips'),
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+ decodetree.process('xlrbr.decode', extra_args: '--static-decode=decode_xlrbr'),
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]
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riscv_ss = ss.source_set()
target/riscv/translate.c
+3
@@ -1213,9 +1213,11 @@ static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc)
1213
#include "insn_trans/trans_rvbf16.c.inc"
1214
#include "decode-xthead.c.inc"
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#include "decode-xmips.c.inc"
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+#include "decode-xlrbr.c.inc"
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#include "insn_trans/trans_xthead.c.inc"
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#include "insn_trans/trans_xventanacondops.c.inc"
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#include "insn_trans/trans_xmips.c.inc"
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+#include "insn_trans/trans_xlrbr.c.inc"
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/* Include the auto-generated decoder for 16 bit insn */
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#include "decode-insn16.c.inc"
@@ -1235,6 +1237,7 @@ const RISCVDecoder decoder_table[] = {
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{ has_xmips_p, decode_xmips},
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{ has_xthead_p, decode_xthead},
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{ has_XVentanaCondOps_p, decode_XVentanaCodeOps},
1240
+ { has_xlrbr_p, decode_xlrbr},
1241
};
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const size_t decoder_table_size = ARRAY_SIZE(decoder_table);
target/riscv/xlrbr.decode
new
+30
@@ -0,0 +1,30 @@
1
+#
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+# Translation routines for the instructions of the xlrbr ISA extension
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+# (matching the draft encodings in the standard reserved encoding space for the
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+# unratified Zbr CRC32 bitmanip extension version 0.93).
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+#
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+# Copyright (c) 2026 Rivos Inc.
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+#
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+# SPDX-License-Identifier: GPL-2.0-or-later
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+
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+# Fields:
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+%rs1 15:5
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+%rd 7:5
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+
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+# Argument sets:
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+&r2 rd rs1 !extern
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+
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+# Formats 32:
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+@r2 ....... ..... ..... ... ..... ....... &r2 %rs1 %rd
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+
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+# *** RV32 xlrbr extension ***
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+crc32_b 0110000 10000 ..... 001 ..... 0010011 @r2
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+crc32_h 0110000 10001 ..... 001 ..... 0010011 @r2
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+crc32_w 0110000 10010 ..... 001 ..... 0010011 @r2
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+crc32c_b 0110000 11000 ..... 001 ..... 0010011 @r2
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+crc32c_h 0110000 11001 ..... 001 ..... 0010011 @r2
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+crc32c_w 0110000 11010 ..... 001 ..... 0010011 @r2
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+
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+# *** RV64 xlrbr extension (in addition to RV32) ***
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+crc32_d 0110000 10011 ..... 001 ..... 0010011 @r2
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+crc32c_d 0110000 11011 ..... 001 ..... 0010011 @r2
tests/tcg/riscv64/Makefile.softmmu-target
+5
@@ -36,5 +36,10 @@ run-plugin-interruptedmemory: interruptedmemory
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$(QEMU) -plugin ../plugins/libdiscons.so -d plugin -D $<.pout \
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$(QEMU_OPTS)$<)
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+EXTRA_RUNS += run-test-crc32
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+comma:= ,
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+run-test-crc32: test-crc32
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+ $(call run-test, $<, $(QEMU) -cpu rv64$(comma)xlrbr=true $(QEMU_OPTS)$<)
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+
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# We don't currently support the multiarch system tests
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undefine MULTIARCH_TESTS
tests/tcg/riscv64/test-crc32.S
new
+64
@@ -0,0 +1,64 @@
1
+/*
2
+ * Copyright (c) 2026 lowRISC CIC
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+ * SPDX-License-Identifier: GPL-2.0-or-later
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+ */
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+
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+#define crc32(op, rd, rs1) .insn r 19, 1, 48, rd, rs1, x##op
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+
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+#define crc32_b(rd, rs1) crc32(16, rd, rs1)
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+#define crc32_h(rd, rs1) crc32(17, rd, rs1)
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+#define crc32_w(rd, rs1) crc32(18, rd, rs1)
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+#define crc32_d(rd, rs1) crc32(19, rd, rs1)
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+#define crc32c_b(rd, rs1) crc32(24, rd, rs1)
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+#define crc32c_h(rd, rs1) crc32(25, rd, rs1)
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+#define crc32c_w(rd, rs1) crc32(26, rd, rs1)
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+#define crc32c_d(rd, rs1) crc32(27, rd, rs1)
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+
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+ .option norvc
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+
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+ .text
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+ .globl _start
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+_start:
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+ lla t0, trap
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+ csrw mtvec, t0
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+
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+ li t0, 0x34e24a2cd65650d4
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+
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+ crc32_b (t0, t0)
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+ crc32_h (t0, t0)
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+ crc32_w (t0, t0)
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+ crc32_d (t0, t0)
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+ crc32c_b (t0, t0)
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+ crc32c_h (t0, t0)
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+ crc32c_w (t0, t0)
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+ crc32c_d (t0, t0)
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+
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+ li t1, 0x68167e78
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+
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+ li a0, 0
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+ beq t0, t1, _exit
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+fail:
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+ li a0, 1
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+_exit:
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+ lla a1, semiargs
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+ li t0, 0x20026 # ADP_Stopped_ApplicationExit
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+ sd t0, 0(a1)
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+ sd a0, 8(a1)
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+ li a0, 0x20 # TARGET_SYS_EXIT_EXTENDED
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+
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+ # Semihosting call sequence
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+ .balign 16
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+ slli zero, zero, 0x1f
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+ ebreak
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+ srai zero, zero, 0x7
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+ j .
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+
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+ .data
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+ .balign 16
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+semiargs:
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+ .space 16
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+
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+trap:
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+ csrr t0, mepc
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+ addi t0, t0, 4
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+ mret