@samitouri / QOSamiQemu / commits / 336c373954

target/riscv: rvv: Add new VTYPE CSR field - altfmt

According to the Zvfbfa ISA spec v0.1, the vtype CSR adds a new field: altfmt for BF16 support. This update changes the layout of the vtype CSR fields. - Removed VEDIV field (bits 8-9) since EDIV extension is not planned to be part of the base V extension - Added ALTFMT field at bit 8 - Changed RESERVED field to start from bit 9 instead of bit 10 When Zvfbfa is disabled, bits 8+ are treated as reserved (preserving existing behavior for altfmt bit). When Zvfbfa is enabled, only bits 9+ are reserved. Reference: - https://github.com/riscvarchive/riscv-v-spec/blob/master/ediv.adoc Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Chao Liu <chao.liu.zevorn@gmail.com> Reviewed-by: Nutty Liu <nutty.liu@hotmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Max Chou <max.chou@sifive.com> Message-ID: <20260402125234.1371897-4-max.chou@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>

Max Chou committed Apr 2, 2026 at 20:52 UTC 336c373954457b3479ca6c02270183f6b9c0e3f4

2 files changed +36 -7

target/riscv/cpu.h

+2 -2

@@ -191,8 +191,8 @@ FIELD(VTYPE, VLMUL, 0, 3)

191 FIELD(VTYPE, VSEW, 3, 3)

192 FIELD(VTYPE, VTA, 6, 1)

193 FIELD(VTYPE, VMA, 7, 1)

194 -FIELD(VTYPE, VEDIV, 8, 2)

195 -FIELD(VTYPE, RESERVED, 10, sizeof(target_ulong) * 8 - 11)

194 +FIELD(VTYPE, ALTFMT, 8, 1)

195 +FIELD(VTYPE, RESERVED, 9, sizeof(target_ulong) * 8 - 10)

196

197 typedef struct PMUCTRState {

198 /* Current value of a counter */

target/riscv/vector_helper.c

+34 -5

@@ -33,6 +33,22 @@

33 #include "vector_internals.h"

34 #include <math.h>

36 +static target_ulong vtype_reserved(CPURISCVState *env, target_ulong vtype)

37 +{

38 + int xlen = riscv_cpu_xlen(env);

39 + target_ulong reserved = 0;

40 +

41 + if (riscv_cpu_cfg(env)->ext_zvfbfa) {

42 + reserved = vtype & MAKE_64BIT_MASK(R_VTYPE_RESERVED_SHIFT,

43 + xlen - 1 - R_VTYPE_RESERVED_SHIFT);

44 + } else {

45 + reserved = vtype & MAKE_64BIT_MASK(R_VTYPE_ALTFMT_SHIFT,

46 + xlen - 1 - R_VTYPE_ALTFMT_SHIFT);

47 + }

48 +

49 + return reserved;

50 +}

51 +

52 target_ulong HELPER(vsetvl)(CPURISCVState *env, target_ulong s1,

53 target_ulong s2, target_ulong x0)

54 {

@@ -41,12 +57,10 @@ target_ulong HELPER(vsetvl)(CPURISCVState *env, target_ulong s1,

57 uint64_t vlmul = FIELD_EX64(s2, VTYPE, VLMUL);

58 uint8_t vsew = FIELD_EX64(s2, VTYPE, VSEW);

59 uint16_t sew = 8 << vsew;

44 - uint8_t ediv = FIELD_EX64(s2, VTYPE, VEDIV);

60 + uint8_t altfmt = FIELD_EX64(s2, VTYPE, ALTFMT);

61 + bool ill_altfmt = true;

62 int xlen = riscv_cpu_xlen(env);

63 bool vill = (s2 >> (xlen - 1)) & 0x1;

47 - target_ulong reserved = s2 &

48 - MAKE_64BIT_MASK(R_VTYPE_RESERVED_SHIFT,

49 - xlen - 1 - R_VTYPE_RESERVED_SHIFT);

64 uint16_t vlen = cpu->cfg.vlenb << 3;

65 int8_t lmul;

@@ -63,7 +77,22 @@ target_ulong HELPER(vsetvl)(CPURISCVState *env, target_ulong s1,

77 }

78 }

66 - if ((sew > cpu->cfg.elen) || vill || (ediv != 0) || (reserved != 0)) {

80 + switch (vsew) {

81 + case MO_8:

82 + ill_altfmt &= !(cpu->cfg.ext_zvfbfa);

83 + break;

84 + case MO_16:

85 + ill_altfmt &= !(cpu->cfg.ext_zvfbfa);

86 + break;

87 + default:

88 + break;

89 + }

90 +

91 + if (altfmt && ill_altfmt) {

92 + vill = true;

93 + }

94 +

95 + if ((sew > cpu->cfg.elen) || vill || (vtype_reserved(env, s2) != 0)) {

96 /* only set vill bit. */

97 env->vill = 1;

98 env->vtype = 0;