target/arm: migrate system/cp trap syndromes to registerfields
Migrate syn_aa64_sysregtrap and co-processor register trap syndromes to the registerfields API. The co-processor syndromes are split between single and duel register moves. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 20260422125250.1303100-3-alex.bennee@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Alex Bennée committed
Apr 22, 2026 at 13:52 UTC
342a587ca2f426beb27cb2fb3ebf476aea5fcdb5
1 file changed
+102
-22
target/arm/syndrome.h
+102
-22
@@ -78,7 +78,7 @@ enum arm_exception_class {
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/* Generic syndrome encoding layout for HSR and lower 32 bits of ESR_EL2 */
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FIELD(SYNDROME, EC, 26, 6)
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-FIELD(SYNDROME, IL, 25, 1)
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+FIELD(SYNDROME, IL, 25, 1) /* IL=1 for 32 bit instructions */
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FIELD(SYNDROME, ISS, 0, 25)
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typedef enum {
@@ -172,7 +172,7 @@ static inline uint32_t syn_aa64_smc(uint32_t imm16)
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static inline uint32_t syn_aa32_svc(uint32_t imm16, bool is_16bit)
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{
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uint32_t res = syn_set_ec(0, EC_AA32_SVC);
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- res = FIELD_DP32(res, SYNDROME, IL, is_16bit ? 0 : 1);
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+ res = FIELD_DP32(res, SYNDROME, IL, !is_16bit);
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res = FIELD_DP32(res, ISS_IMM16, IMM16, imm16);
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return res;
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}
@@ -203,58 +203,138 @@ static inline uint32_t syn_aa64_bkpt(uint32_t imm16)
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static inline uint32_t syn_aa32_bkpt(uint32_t imm16, bool is_16bit)
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{
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uint32_t res = syn_set_ec(0, EC_AA32_BKPT);
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- res = FIELD_DP32(res, SYNDROME, IL, is_16bit ? 0 : 1);
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+ res = FIELD_DP32(res, SYNDROME, IL, !is_16bit);
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res = FIELD_DP32(res, ISS_IMM16, IMM16, imm16);
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return res;
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}
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+/*
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+ * ISS encoding for an exception from MSR, MRS, or System instruction
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+ * in AArch64 state.
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+ */
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+FIELD(SYSREG_ISS, ISREAD, 0, 1) /* Direction, 1 is read */
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+FIELD(SYSREG_ISS, CRM, 1, 4)
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+FIELD(SYSREG_ISS, RT, 5, 5)
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+FIELD(SYSREG_ISS, CRN, 10, 4)
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+FIELD(SYSREG_ISS, OP1, 14, 3)
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+FIELD(SYSREG_ISS, OP2, 17, 3)
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+FIELD(SYSREG_ISS, OP0, 20, 2)
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+
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static inline uint32_t syn_aa64_sysregtrap(int op0, int op1, int op2,
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int crn, int crm, int rt,
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int isread)
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{
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- return (EC_SYSTEMREGISTERTRAP << ARM_EL_EC_SHIFT) | ARM_EL_IL
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- | (op0 << 20) | (op2 << 17) | (op1 << 14) | (crn << 10) | (rt << 5)
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- | (crm << 1) | isread;
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+ uint32_t res = syn_set_ec(0, EC_SYSTEMREGISTERTRAP);
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+ res = FIELD_DP32(res, SYNDROME, IL, 1);
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+
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+ res = FIELD_DP32(res, SYSREG_ISS, OP0, op0);
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+ res = FIELD_DP32(res, SYSREG_ISS, OP2, op2);
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+ res = FIELD_DP32(res, SYSREG_ISS, OP1, op1);
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+ res = FIELD_DP32(res, SYSREG_ISS, CRN, crn);
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+ res = FIELD_DP32(res, SYSREG_ISS, RT, rt);
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+ res = FIELD_DP32(res, SYSREG_ISS, CRM, crm);
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+ res = FIELD_DP32(res, SYSREG_ISS, ISREAD, isread);
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+
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+ return res;
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}
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+/*
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+ * ISS encoding for an exception from an MCR or MRC access
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+ * (move to/from co-processor)
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+ */
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+FIELD(COPROC_ISS, ISREAD, 0, 1)
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+FIELD(COPROC_ISS, CRM, 1, 4)
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+FIELD(COPROC_ISS, RT, 5, 5)
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+FIELD(COPROC_ISS, CRN, 10, 4)
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+FIELD(COPROC_ISS, OP1, 14, 3)
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+FIELD(COPROC_ISS, OP2, 17, 3)
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+FIELD(COPROC_ISS, COND, 20, 4)
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+FIELD(COPROC_ISS, CV, 24, 1)
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+
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static inline uint32_t syn_cp14_rt_trap(int cv, int cond, int opc1, int opc2,
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int crn, int crm, int rt, int isread,
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bool is_16bit)
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{
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- return (EC_CP14RTTRAP << ARM_EL_EC_SHIFT)
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- | (is_16bit ? 0 : ARM_EL_IL)
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- | (cv << 24) | (cond << 20) | (opc2 << 17) | (opc1 << 14)
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- | (crn << 10) | (rt << 5) | (crm << 1) | isread;
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+ uint32_t res = syn_set_ec(0, EC_CP14RTTRAP);
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+ res = FIELD_DP32(res, SYNDROME, IL, !is_16bit);
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+
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+ res = FIELD_DP32(res, COPROC_ISS, CV, cv);
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+ res = FIELD_DP32(res, COPROC_ISS, COND, cond);
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+ res = FIELD_DP32(res, COPROC_ISS, OP2, opc2);
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+ res = FIELD_DP32(res, COPROC_ISS, OP1, opc1);
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+ res = FIELD_DP32(res, COPROC_ISS, CRN, crn);
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+ res = FIELD_DP32(res, COPROC_ISS, RT, rt);
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+ res = FIELD_DP32(res, COPROC_ISS, CRM, crm);
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+ res = FIELD_DP32(res, COPROC_ISS, ISREAD, isread);
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+
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+ return res;
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}
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static inline uint32_t syn_cp15_rt_trap(int cv, int cond, int opc1, int opc2,
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int crn, int crm, int rt, int isread,
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bool is_16bit)
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{
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- return (EC_CP15RTTRAP << ARM_EL_EC_SHIFT)
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- | (is_16bit ? 0 : ARM_EL_IL)
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- | (cv << 24) | (cond << 20) | (opc2 << 17) | (opc1 << 14)
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- | (crn << 10) | (rt << 5) | (crm << 1) | isread;
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+ uint32_t res = syn_set_ec(0, EC_CP15RTTRAP);
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+ res = FIELD_DP32(res, SYNDROME, IL, !is_16bit);
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+
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+ res = FIELD_DP32(res, COPROC_ISS, CV, cv);
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+ res = FIELD_DP32(res, COPROC_ISS, COND, cond);
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+ res = FIELD_DP32(res, COPROC_ISS, OP2, opc2);
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+ res = FIELD_DP32(res, COPROC_ISS, OP1, opc1);
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+ res = FIELD_DP32(res, COPROC_ISS, CRN, crn);
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+ res = FIELD_DP32(res, COPROC_ISS, RT, rt);
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+ res = FIELD_DP32(res, COPROC_ISS, CRM, crm);
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+ res = FIELD_DP32(res, COPROC_ISS, ISREAD, isread);
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+
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+ return res;
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}
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+/*
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+ * ISS encoding for an exception from an MCRR or MRRC access
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+ * (move to/from co-processor with 2 regs)
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+ */
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+FIELD(COPROC_R2_ISS, ISREAD, 0, 1)
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+FIELD(COPROC_R2_ISS, CRM, 1, 4)
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+FIELD(COPROC_R2_ISS, RT, 5, 5)
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+FIELD(COPROC_R2_ISS, RT2, 10, 5)
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+FIELD(COPROC_R2_ISS, OP1, 16, 4)
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+FIELD(COPROC_R2_ISS, COND, 20, 4)
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+FIELD(COPROC_R2_ISS, CV, 24, 1)
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+
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static inline uint32_t syn_cp14_rrt_trap(int cv, int cond, int opc1, int crm,
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int rt, int rt2, int isread,
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bool is_16bit)
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{
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- return (EC_CP14RRTTRAP << ARM_EL_EC_SHIFT)
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- | (is_16bit ? 0 : ARM_EL_IL)
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- | (cv << 24) | (cond << 20) | (opc1 << 16)
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- | (rt2 << 10) | (rt << 5) | (crm << 1) | isread;
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+ uint32_t res = syn_set_ec(0, EC_CP14RRTTRAP);
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+ res = FIELD_DP32(res, SYNDROME, IL, !is_16bit);
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+
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+ res = FIELD_DP32(res, COPROC_R2_ISS, CV, cv);
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+ res = FIELD_DP32(res, COPROC_R2_ISS, COND, cond);
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+ res = FIELD_DP32(res, COPROC_R2_ISS, OP1, opc1);
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+ res = FIELD_DP32(res, COPROC_R2_ISS, RT2, rt2);
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+ res = FIELD_DP32(res, COPROC_R2_ISS, RT, rt);
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+ res = FIELD_DP32(res, COPROC_R2_ISS, CRM, crm);
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+ res = FIELD_DP32(res, COPROC_R2_ISS, ISREAD, isread);
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+
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+ return res;
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}
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static inline uint32_t syn_cp15_rrt_trap(int cv, int cond, int opc1, int crm,
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int rt, int rt2, int isread,
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bool is_16bit)
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{
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- return (EC_CP15RRTTRAP << ARM_EL_EC_SHIFT)
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- | (is_16bit ? 0 : ARM_EL_IL)
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- | (cv << 24) | (cond << 20) | (opc1 << 16)
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- | (rt2 << 10) | (rt << 5) | (crm << 1) | isread;
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+ uint32_t res = syn_set_ec(0, EC_CP15RRTTRAP);
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+ res = FIELD_DP32(res, SYNDROME, IL, !is_16bit);
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+
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+ res = FIELD_DP32(res, COPROC_R2_ISS, CV, cv);
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+ res = FIELD_DP32(res, COPROC_R2_ISS, COND, cond);
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+ res = FIELD_DP32(res, COPROC_R2_ISS, OP1, opc1);
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+ res = FIELD_DP32(res, COPROC_R2_ISS, RT2, rt2);
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+ res = FIELD_DP32(res, COPROC_R2_ISS, RT, rt);
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+ res = FIELD_DP32(res, COPROC_R2_ISS, CRM, crm);
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+ res = FIELD_DP32(res, COPROC_R2_ISS, ISREAD, isread);
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+
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+ return res;
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}
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static inline uint32_t syn_fp_access_trap(int cv, int cond, bool is_16bit,