target/arm: GICv5 cpuif: Implement PPI handling mode register
In the GICv5 the handling mode of a PPI is not software configurable; it is reported via read-only CPU interface registers ICC_PPI_HMR0_EL1 and ICC_PPI_HMR1_EL1. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com> Message-id: 20260327111700.795099-38-peter.maydell@linaro.org
Peter Maydell committed
Mar 27, 2026 at 11:16 UTC
394ad2e928c571cfbd202c562b220cca7d555707
2 files changed
+23
target/arm/cpu.h
+1
@@ -604,6 +604,7 @@ typedef struct CPUArchState {
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uint64_t icc_icsr_el1;
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/* Most PPI registers have 1 bit per PPI, so 64 PPIs to a register */
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uint64_t ppi_active[GICV5_NUM_PPIS / 64];
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+ uint64_t ppi_hm[GICV5_NUM_PPIS / 64];
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} gicv5_cpuif;
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struct {
target/arm/tcg/gicv5-cpuif.c
+22
@@ -50,6 +50,16 @@ FIELD(ICC_IDR0_EL1, GCIE_LEGACY, 8, 4)
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((4 << R_ICC_IDR0_EL1_PRI_BITS_SHIFT) | \
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(1 << R_ICC_IDR0_EL1_ID_BITS_SHIFT))
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+/*
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+ * PPI handling modes are fixed and not software configurable.
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+ * R_CFSKX defines them for the architected PPIs: they are all Level,
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+ * except that PPI 24 (CTIIRQ) is IMPDEF and PPI 3 (SW_PPI) is Edge.
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+ * For unimplemented PPIs the field is RES0. The PPI register bits
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+ * are 1 for Level and 0 for Edge.
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+ */
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+#define PPI_HMR0_RESET (~(1ULL << GICV5_PPI_SW_PPI))
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+#define PPI_HMR1_RESET (~0ULL)
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+
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static GICv5Common *gicv5_get_gic(CPUARMState *env)
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{
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return env->gicv5state;
@@ -292,6 +302,18 @@ static const ARMCPRegInfo gicv5_cpuif_reginfo[] = {
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.fieldoffset = offsetof(CPUARMState, gicv5_cpuif.ppi_active[1]),
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.writefn = gic_ppi_sactive_write,
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},
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+ { .name = "ICC_PPI_HMR0_EL1", .state = ARM_CP_STATE_AA64,
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+ .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 10, .opc2 = 0,
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+ .access = PL1_R, .type = ARM_CP_IO | ARM_CP_NO_RAW,
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+ .fieldoffset = offsetof(CPUARMState, gicv5_cpuif.ppi_hm[0]),
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+ .resetvalue = PPI_HMR0_RESET,
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+ },
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+ { .name = "ICC_PPI_HMR1_EL1", .state = ARM_CP_STATE_AA64,
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+ .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 10, .opc2 = 1,
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+ .access = PL1_R, .type = ARM_CP_IO | ARM_CP_NO_RAW,
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+ .fieldoffset = offsetof(CPUARMState, gicv5_cpuif.ppi_hm[1]),
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+ .resetvalue = PPI_HMR1_RESET,
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+ },
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};
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void define_gicv5_cpuif_regs(ARMCPU *cpu)