target/riscv: Introduce BF16 canonical NaN for Zvfbfa extension
According to the Zvfbfa ISA spec (v0.1), improperly NaN-boxed f-register operands must substitute the BF16 canonical NaN instead of the FP16 canonical NaN for some vector floating-point instructions. Reviewed-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com> Reviewed-by: Chao Liu <chao.liu.zevorn@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Max Chou <max.chou@sifive.com> Message-ID: <20260402125234.1371897-8-max.chou@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Max Chou committed
Apr 2, 2026 at 20:52 UTC
39a5ec3001b4ef45aae32338d6ec000766cae753
2 files changed
+17
-9
target/riscv/insn_trans/trans_rvv.c.inc
+9
-9
@@ -2319,17 +2319,17 @@ GEN_OPIWI_NARROW_TRANS(vnclip_wi, IMM_ZX, vnclip_wx)
2319
*/
2320
static void do_nanbox(DisasContext *s, TCGv_i64 out, TCGv_i64 in)
2321
{
2322
- switch (s->sew) {
2323
- case 1:
2324
- gen_check_nanbox_h(out, in);
2325
- break;
2326
- case 2:
2322
+ if (s->sew == MO_16) {
2323
+ if (s->altfmt) {
2324
+ gen_check_nanbox_h_bf16(out, in);
2325
+ } else {
2326
+ gen_check_nanbox_h(out, in);
2327
+ }
2328
+ } else if (s->sew == MO_32) {
2329
gen_check_nanbox_s(out, in);
2328
- break;
2329
- case 3:
2330
+ } else if (s->sew == MO_64) {
2331
tcg_gen_mov_i64(out, in);
2331
- break;
2332
- default:
2332
+ } else {
2333
g_assert_not_reached();
2334
}
2335
}
target/riscv/translate.c
+8
@@ -214,6 +214,14 @@ static void gen_check_nanbox_h(TCGv_i64 out, TCGv_i64 in)
214
tcg_gen_movcond_i64(TCG_COND_GEU, out, in, t_max, in, t_nan);
215
}
216
217
+static void gen_check_nanbox_h_bf16(TCGv_i64 out, TCGv_i64 in)
218
+{
219
+ TCGv_i64 t_max = tcg_constant_i64(0xffffffffffff0000ull);
220
+ TCGv_i64 t_nan = tcg_constant_i64(0xffffffffffff7fc0ull);
221
+
222
+ tcg_gen_movcond_i64(TCG_COND_GEU, out, in, t_max, in, t_nan);
223
+}
224
+
225
static void gen_check_nanbox_s(TCGv_i64 out, TCGv_i64 in)
226
{
227
TCGv_i64 t_max = tcg_constant_i64(0xffffffff00000000ull);