@samitouri / QOSamiQemu / commits / 49e082a813

target/riscv: add Zvknha as an implied extension for Zvknhb

The RISC-V unpriv specification (zvk.adoc) states that "Zvknhb implies Zvknha". This means that enabling Zvknhb should automatically enable Zvknha. Add Zvknha to ZVKNHB_IMPLIED to ensure the dependency is correctly enforced. This issue was discovered and reported by SpecHunter, an AI-driven architecture specification analysis tool. Link:https://github.com/yizishun/rv-isa-sec/blob/master/output/riscv-isa-manual/pr-2635/qemu.txt Signed-off-by: Zishun Yi <vulab@iscas.ac.cn> Reviewed-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com> Message-ID: <20260511051736.2916225-1-vulab@iscas.ac.cn> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>

Zishun Yi committed May 11, 2026 at 13:17 UTC 49e082a813193646fbab2732af61fc0091daf2a7
1 file changed +1 -1
target/riscv/cpu.c
+1 -1
@@ -2542,7 +2542,7 @@ static RISCVCPUImpliedExtsRule ZVKNG_IMPLIED = {
2542 static RISCVCPUImpliedExtsRule ZVKNHB_IMPLIED = {
2543 .ext = CPU_CFG_OFFSET(ext_zvknhb),
2544 .implied_multi_exts = {
2545 - CPU_CFG_OFFSET(ext_zve64x),
2545 + CPU_CFG_OFFSET(ext_zve64x), CPU_CFG_OFFSET(ext_zvknha),
2546
2547 RISCV_IMPLIED_EXTS_RULE_END
2548 },