target/riscv: rvv: Handle mask/source overlap of vector reduction instructions
Masked vector reduction instructions must not use v0 as a source register. Check rs1 and rs2 against the mask register when vm=0. Signed-off-by: Anton Blanchard <antonb@tenstorrent.com> Reviewed-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com> Message-ID: <20260417120626.77415-1-antonb@tenstorrent.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Anton Blanchard committed
Apr 17, 2026 at 12:06 UTC
4d82676cfc6e14099d0e529445a5ee520752ebe5
1 file changed
+2
target/riscv/insn_trans/trans_rvv.c.inc
+2
@@ -3265,6 +3265,8 @@ static bool reduction_check(DisasContext *s, arg_rmrr *a)
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{
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return require_rvv(s) &&
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vext_check_isa_ill(s) &&
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+ require_vm(a->vm, a->rs1) &&
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+ require_vm(a->vm, a->rs2) &&
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vext_check_reduction(s, a->rs2);
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}
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