target/mips: Do not initialize variable used by CPU_FOREACH macro
The CPU_FOREACH() macro, defined in "hw/core/cpu.h", ends up calling QTAILQ_FOREACH_RCU() which always assigns its iterator variable when entering the loop. Remove the pointless and possibly misleading assignment. Mechanical patch using the following coccinelle spatch: @@ type T; identifier e; iterator FOREACH_MACRO =~ ".*_FOREACH.*"; statement S; @@ - T *e = ...; + T *e; ... when != e FOREACH_MACRO(e, ...) S Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com> Message-Id: <20260415215539.92629-7-philmd@linaro.org>
Philippe Mathieu-Daudé committed
May 6, 2026 at 14:42 UTC
4ed05237df2bde45a7058239794c1da230197c58
4 files changed
+8
-8
hw/misc/mips_cpc.c
+2
-2
@@ -45,7 +45,7 @@ static void mips_cpu_reset_async_work(CPUState *cs, run_on_cpu_data data)
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static void cpc_run_vp(MIPSCPCState *cpc, uint64_t vp_run)
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{
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- CPUState *cs = first_cpu;
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+ CPUState *cs;
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CPU_FOREACH(cs) {
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uint64_t i = 1ULL << cs->cpu_index;
@@ -63,7 +63,7 @@ static void cpc_run_vp(MIPSCPCState *cpc, uint64_t vp_run)
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static void cpc_stop_vp(MIPSCPCState *cpc, uint64_t vp_stop)
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{
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- CPUState *cs = first_cpu;
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+ CPUState *cs;
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CPU_FOREACH(cs) {
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uint64_t i = 1ULL << cs->cpu_index;
target/mips/internal.h
+1
-1
@@ -280,7 +280,7 @@ static inline int mips_vpe_active(CPUMIPSState *env)
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static inline int mips_vp_active(CPUMIPSState *env)
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{
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- CPUState *cs = first_cpu;
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+ CPUState *cs;
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/* Check if the VP disabled other VPs (which means the VP is enabled) */
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if ((env->CP0_VPControl >> CP0VPCtl_DIS) & 1) {
target/mips/tcg/system/cp0_helper.c
+4
-4
@@ -1570,7 +1570,7 @@ target_ulong helper_dvpe(CPUMIPSState *env)
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target_ulong prev = cpu->mvp->CP0_MVPControl;
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if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) {
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- CPUState *cs = first_cpu;
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+ CPUState *cs;
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CPU_FOREACH(cs) {
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MIPSCPU *other_cpu = MIPS_CPU(cs);
@@ -1590,7 +1590,7 @@ target_ulong helper_evpe(CPUMIPSState *env)
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target_ulong prev = cpu->mvp->CP0_MVPControl;
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if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) {
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- CPUState *cs = first_cpu;
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+ CPUState *cs;
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CPU_FOREACH(cs) {
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MIPSCPU *other_cpu = MIPS_CPU(cs);
@@ -1613,7 +1613,7 @@ target_ulong helper_dvp(CPUMIPSState *env)
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target_ulong prev = env->CP0_VPControl;
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if (!((env->CP0_VPControl >> CP0VPCtl_DIS) & 1)) {
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- CPUState *cpu = first_cpu;
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+ CPUState *cpu;
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CPU_FOREACH(cpu) {
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MIPSCPU *other_cpu = MIPS_CPU(cpu);
@@ -1632,7 +1632,7 @@ target_ulong helper_evp(CPUMIPSState *env)
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target_ulong prev = env->CP0_VPControl;
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if ((env->CP0_VPControl >> CP0VPCtl_DIS) & 1) {
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- CPUState *cpu = first_cpu;
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+ CPUState *cpu;
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CPU_FOREACH(cpu) {
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MIPSCPU *other_cpu = MIPS_CPU(cpu);
target/mips/tcg/system/tlb_helper.c
+1
-1
@@ -346,7 +346,7 @@ void helper_ginvt(CPUMIPSState *env, target_ulong arg, uint32_t type)
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uint32_t invMsgVPN2 = arg & (TARGET_PAGE_MASK << 1);
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uint8_t invMsgR = 0;
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uint32_t invMsgMMid = env->CP0_MemoryMapID;
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- CPUState *cpu = first_cpu;
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+ CPUState *cpu;
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#ifdef TARGET_MIPS64
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invMsgR = extract64(arg, 62, 2);