@samitouri / QOSamiQemu / commits / 51be584f03

target/riscv: Use MO_LE for instruction fetch

RISC-V instructions are always little-endian regardless of the data endianness mode configured via mstatus SBE/MBE/UBE bits. Currently, instruction fetches in decode_opc() and the page boundary check use mo_endian(ctx), which returns MO_TE. This happens to work today because RISC-V targets are little-endian only, but is semantically incorrect and will break once mo_endian() is updated to respect runtime data endianness for big-endian support. Use MO_LE explicitly for all instruction fetch paths. Data memory operations (AMOs, loads/stores via mxl_memop) continue to use mo_endian(ctx) as they should respect the configured data endianness. Not-Signed-off-by: Djordje Todorovic <Djordje.Todorovic@htecgroup.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20260311115910.564481-3-djordje.todorovic@htecgroup.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20260318103122.97244-16-philmd@linaro.org> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>

Djordje Todorovic committed Mar 18, 2026 at 11:31 UTC 51be584f0358d892862e5462fae4a36efaaf02b9

1 file changed +4 -4

target/riscv/translate.c

+4 -4

@@ -1258,7 +1258,7 @@ static void decode_opc(CPURISCVState *env, DisasContext *ctx)

1258 * additional page fault.

1259 */

1260 opcode = translator_ldl_end(env, &ctx->base, ctx->base.pc_next,

1261 - mo_endian(ctx));

1261 + MO_LE);

1262 } else {

1263 /*

1264 * For unaligned pc, instruction preload may trigger additional

@@ -1266,7 +1266,7 @@ static void decode_opc(CPURISCVState *env, DisasContext *ctx)

1266 */

1267 opcode = (uint32_t) translator_lduw_end(env, &ctx->base,

1268 ctx->base.pc_next,

1269 - mo_endian(ctx));

1269 + MO_LE);

1270 }

1271 ctx->ol = ctx->xl;

1272

@@ -1288,7 +1288,7 @@ static void decode_opc(CPURISCVState *env, DisasContext *ctx)

1288 opcode = deposit32(opcode, 16, 16,

1289 translator_lduw_end(env, &ctx->base,

1290 ctx->base.pc_next + 2,

1291 - mo_endian(ctx)));

1291 + MO_LE));

1292 }

1293 ctx->opcode = opcode;

1294

@@ -1404,7 +1404,7 @@ static void riscv_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)

1404 if (page_ofs > TARGET_PAGE_SIZE - MAX_INSN_LEN) {

1405 uint16_t next_insn =

1406 translator_lduw_end(env, &ctx->base, ctx->base.pc_next,

1407 - mo_endian(ctx));

1407 + MO_LE);

1408 int len = insn_len(next_insn);

1409

1410 if (!translator_is_same_page(&ctx->base, ctx->base.pc_next + len - 1)) {