hvf: arm: allow exposing minimal PMU for kernel-irqchip=on
When running with the Apple vGIC, a minimum PMU is exposed by Hypervisor.framework if a valid PMUVer register value is set. That PMU isn't exposed otherwise. Signed-off-by: Mohamed Mediouni <mohamed@unpredictable.fr> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20260429190532.26538-9-mohamed@unpredictable.fr Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Mohamed Mediouni committed
May 5, 2026 at 09:25 UTC
520320720a11a61d91bbf691564dfcd4956418a9
1 file changed
+19
target/arm/hvf/hvf.c
+19
@@ -1145,6 +1145,25 @@ static bool hvf_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
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clamp_id_aa64mmfr0_parange_to_ipa_size(&host_isar);
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+ /*
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+ * Windows wants at least the PMU's cycles counter to be available.
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+ *
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+ * With kernel-irqchip=off, we "emulate" the cycles counter
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+ * in reference to time in QEMU. Having that, even with
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+ * ID_AA64DFR0_EL1.PMUVer = 0 is enough to make Windows happy.
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+ *
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+ * As it's a very inaccurate implementation with its only purpose
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+ * being making Windows boot, expose ID_AA64DFR0_EL1.PMUVer = 0
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+ * when kernel-irqchip=off.
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+ *
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+ * When kernel-irqchip=on *and* ID_AA64DFR0_EL1.PMUVer = 1,
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+ * the OS provides its own PMU emulation, which is currently
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+ * a cycles counter only emulation.
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+ */
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+ if (hvf_irqchip_in_kernel()) {
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+ FIELD_DP64_IDREG(&host_isar, ID_AA64DFR0, PMUVER, 0x1);
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+ }
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+
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ahcf->isar = host_isar;
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/*