@samitouri / QOSamiQemu / commits / 52c951c1ae

target/riscv: Introduce altfmt into DisasContext

Reviewed-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com> Reviewed-by: Chao Liu <chao.liu.zevorn@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Max Chou <max.chou@sifive.com> Message-ID: <20260402125234.1371897-7-max.chou@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>

Max Chou committed Apr 2, 2026 at 20:52 UTC 52c951c1aef3f150756d0c8ac8308628af4e2d1b

1 file changed +3

target/riscv/translate.c

@@ -101,6 +101,7 @@ typedef struct DisasContext {

101 bool cfg_vta_all_1s;

102 bool vstart_eq_zero;

103 bool vl_eq_vlmax;

104 + bool altfmt;

105 CPUState *cs;

106 TCGv zero;

107 /* actual address width */

@@ -1310,6 +1311,7 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)

1311 RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cs);

1312 RISCVCPU *cpu = RISCV_CPU(cs);

1313 uint32_t tb_flags = ctx->base.tb->flags;

1314 + uint64_t ext_tb_flags = ctx->base.tb->cs_base;

1315

1316 ctx->pc_save = ctx->base.pc_first;

1317 ctx->priv = FIELD_EX32(tb_flags, TB_FLAGS, PRIV);

@@ -1329,6 +1331,7 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)

1331 ctx->cfg_vta_all_1s = cpu->cfg.rvv_ta_all_1s;

1332 ctx->vstart_eq_zero = FIELD_EX32(tb_flags, TB_FLAGS, VSTART_EQ_ZERO);

1333 ctx->vl_eq_vlmax = FIELD_EX32(tb_flags, TB_FLAGS, VL_EQ_VLMAX);

1334 + ctx->altfmt = FIELD_EX64(ext_tb_flags, EXT_TB_FLAGS, ALTFMT);

1335 ctx->misa_mxl_max = mcc->def->misa_mxl_max;

1336 ctx->xl = FIELD_EX32(tb_flags, TB_FLAGS, XL);

1337 ctx->address_xl = FIELD_EX32(tb_flags, TB_FLAGS, AXL);