target/loongarch: Introduce loongarch_palen_mask()
In preparation for dropping TARGET_PHYS_ADDR_SPACE_BITS, define a runtime function to construct a mask from the PALEN cpucfg field. The mask is then used when converting from virtual to physical addresses. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Anton Johansson <anjo@rev.ng> Message-ID: <20260218-phys_addr-v6-4-a603bf363218@rev.ng> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Anton Johansson committed
Dec 9, 2025 at 14:56 UTC
56599a705f24a4a0c100f08bc77799cce8013740
4 files changed
+21
-8
target/loongarch/cpu-mmu.h
+1
@@ -98,5 +98,6 @@ TLBRet loongarch_ptw(CPULoongArchState *env, MMUContext *context,
98
void get_dir_base_width(CPULoongArchState *env, uint64_t *dir_base,
99
uint64_t *dir_width, unsigned int level);
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hwaddr loongarch_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
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+uint64_t loongarch_palen_mask(CPULoongArchState *env);
102
103
#endif /* LOONGARCH_CPU_MMU_H */
target/loongarch/cpu_helper.c
+12
-3
@@ -147,6 +147,7 @@ TLBRet loongarch_ptw(CPULoongArchState *env, MMUContext *context,
147
{
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CPUState *cs = env_cpu(env);
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hwaddr index = 0, phys = 0;
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+ uint64_t palen_mask = loongarch_palen_mask(env);
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uint64_t dir_base, dir_width;
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uint64_t base, pte;
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int level;
@@ -154,13 +155,14 @@ TLBRet loongarch_ptw(CPULoongArchState *env, MMUContext *context,
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TLBRet ret;
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MemTxResult ret1;
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+
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address = context->addr;
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if ((address >> 63) & 0x1) {
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base = env->CSR_PGDH;
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} else {
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base = env->CSR_PGDL;
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}
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- base &= TARGET_PHYS_MASK;
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+ base &= palen_mask;
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for (level = 4; level >= 0; level--) {
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get_dir_base_width(env, &dir_base, &dir_width, level);
@@ -181,7 +183,7 @@ TLBRet loongarch_ptw(CPULoongArchState *env, MMUContext *context,
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break;
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} else {
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/* Discard high bits with page directory table */
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- base &= TARGET_PHYS_MASK;
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+ base &= palen_mask;
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}
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}
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}
@@ -315,7 +317,7 @@ TLBRet get_physical_address(CPULoongArchState *env, MMUContext *context,
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/* Check PG and DA */
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address = context->addr;
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if (da & !pg) {
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- context->physical = address & TARGET_PHYS_MASK;
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+ context->physical = address & loongarch_palen_mask(env);
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context->prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
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context->mmu_index = MMU_DA_IDX;
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return TLBRET_MATCH;
@@ -364,3 +366,10 @@ hwaddr loongarch_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
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}
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return context.physical;
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}
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+
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+uint64_t loongarch_palen_mask(CPULoongArchState *env)
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+{
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+ /* PALEN stores physical address bits - 1 */
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+ uint64_t phys_bits = FIELD_EX32(env->cpucfg[1], CPUCFG1, PALEN) + 1;
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+ return MAKE_64BIT_MASK(0, phys_bits);
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+}
target/loongarch/internals.h
-1
@@ -13,7 +13,6 @@
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#define FCMP_UN 0b0100 /* unordered */
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#define FCMP_GT 0b1000 /* fp0 > fp1 */
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-#define TARGET_PHYS_MASK MAKE_64BIT_MASK(0, TARGET_PHYS_ADDR_SPACE_BITS)
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#define TARGET_VIRT_MASK MAKE_64BIT_MASK(0, TARGET_VIRT_ADDR_SPACE_BITS)
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18
void loongarch_translate_init(void);
target/loongarch/tcg/tlb_helper.c
+8
-4
@@ -692,8 +692,10 @@ target_ulong helper_lddir(CPULoongArchState *env, target_ulong base,
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CPUState *cs = env_cpu(env);
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uint64_t badvaddr;
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hwaddr index, phys;
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+ uint64_t palen_mask = loongarch_palen_mask(env);
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uint64_t dir_base, dir_width;
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+
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if (unlikely((level == 0) || (level > 4))) {
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qemu_log_mask(LOG_GUEST_ERROR,
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"Attepted LDDIR with level %u\n", level);
@@ -715,11 +717,11 @@ target_ulong helper_lddir(CPULoongArchState *env, target_ulong base,
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}
718
719
badvaddr = env->CSR_TLBRBADV;
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- base = base & TARGET_PHYS_MASK;
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+ base = base & palen_mask;
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get_dir_base_width(env, &dir_base, &dir_width, level);
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index = (badvaddr >> dir_base) & ((1 << dir_width) - 1);
723
phys = base | index << 3;
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- return ldq_le_phys(cs->as, phys) & TARGET_PHYS_MASK;
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+ return ldq_le_phys(cs->as, phys) & palen_mask;
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}
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void helper_ldpte(CPULoongArchState *env, target_ulong base, target_ulong odd,
@@ -730,9 +732,11 @@ void helper_ldpte(CPULoongArchState *env, target_ulong base, target_ulong odd,
732
uint64_t badv;
733
uint64_t ptbase = FIELD_EX64(env->CSR_PWCL, CSR_PWCL, PTBASE);
734
uint64_t ptwidth = FIELD_EX64(env->CSR_PWCL, CSR_PWCL, PTWIDTH);
735
+ uint64_t palen_mask = loongarch_palen_mask(env);
736
uint64_t dir_base, dir_width;
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uint8_t ps;
738
739
+
740
/*
741
* The parameter "base" has only two types,
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* one is the page table base address,
@@ -740,7 +744,7 @@ void helper_ldpte(CPULoongArchState *env, target_ulong base, target_ulong odd,
744
* and the other is the huge page entry,
745
* whose bit 6 should be 1.
746
*/
743
- base = base & TARGET_PHYS_MASK;
747
+ base = base & palen_mask;
748
if (FIELD_EX64(base, TLBENTRY, HUGE)) {
749
/*
750
* Gets the huge page level and Gets huge page size.
@@ -781,7 +785,7 @@ void helper_ldpte(CPULoongArchState *env, target_ulong base, target_ulong odd,
785
ptoffset0 = ptindex << 3;
786
ptoffset1 = (ptindex + 1) << 3;
787
phys = base | (odd ? ptoffset1 : ptoffset0);
784
- tmp0 = ldq_le_phys(cs->as, phys) & TARGET_PHYS_MASK;
788
+ tmp0 = ldq_le_phys(cs->as, phys) & palen_mask;
789
ps = ptbase;
790
}
791