hw/intc/arm_gicv5: Implement Deactivate command
Implement the equivalent of the GICv5 stream protocol's Deactivate command, which lets the cpuif tell the IRS to deactivate the specified interrupt. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com> Message-id: 20260327111700.795099-51-peter.maydell@linaro.org
Peter Maydell committed
Mar 27, 2026 at 11:16 UTC
576891bc313ebfdff04b3428818404c3be3a264e
3 files changed
+67
hw/intc/arm_gicv5.c
+52
@@ -1153,6 +1153,58 @@ void gicv5_activate(GICv5Common *cs, uint32_t id, GICv5Domain domain,
1153
irs_recalc_hppi(s, domain, iaffid);
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}
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+void gicv5_deactivate(GICv5Common *cs, uint32_t id, GICv5Domain domain,
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+ GICv5IntType type, bool virtual)
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+{
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+ GICv5 *s = ARM_GICV5(cs);
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+ uint32_t iaffid;
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+
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+ trace_gicv5_deactivate(domain_name[domain], inttype_name(type), virtual, id);
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+
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+ if (virtual) {
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+ qemu_log_mask(LOG_GUEST_ERROR, "gicv5_deactivate: tried to "
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+ "deactivate a virtual interrupt\n");
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+ return;
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+ }
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+
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+ switch (type) {
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+ case GICV5_LPI:
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+ {
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+ const GICv5ISTConfig *cfg = &s->phys_lpi_config[domain];
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+ L2_ISTE_Handle h;
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+ uint32_t *l2_iste_p = get_l2_iste(cs, cfg, id, &h);
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+
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+ if (!l2_iste_p) {
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+ return;
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+ }
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+ *l2_iste_p = FIELD_DP32(*l2_iste_p, L2_ISTE, ACTIVE, false);
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+ iaffid = FIELD_EX32(*l2_iste_p, L2_ISTE, IAFFID);
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+ put_l2_iste(cs, cfg, &h);
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+ break;
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+ }
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+ case GICV5_SPI:
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+ {
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+ GICv5SPIState *spi = gicv5_spi_state(cs, id, domain);
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+
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+ if (!spi) {
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+ qemu_log_mask(LOG_GUEST_ERROR, "gicv5_deactivate: tried to "
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+ "deactivate unreachable SPI %d\n", id);
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+ return;
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+ }
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+
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+ spi->active = false;
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+ iaffid = spi->iaffid;
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+ break;
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+ }
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+ default:
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+ qemu_log_mask(LOG_GUEST_ERROR, "gicv5_deactivate: tried to "
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+ "deactivate bad interrupt type %d\n", type);
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+ return;
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+ }
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+
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+ irs_recalc_hppi(s, domain, iaffid);
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+}
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+
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static void irs_map_l2_istr_write(GICv5 *s, GICv5Domain domain, uint64_t value)
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{
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GICv5Common *cs = ARM_GICV5_COMMON(s);
hw/intc/trace-events
+1
@@ -242,6 +242,7 @@ gicv5_set_handling(const char *domain, const char *type, bool virtual, uint32_t
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gicv5_set_target(const char *domain, const char *type, bool virtual, uint32_t id, uint32_t iaffid, int irm) "GICv5 IRS SetTarget %s %s virtual:%d ID %u IAFFID %u routingmode %d"
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gicv5_request_config(const char *domain, const char *type, bool virtual, uint32_t id, uint64_t icsr) "GICv5 IRS RequestConfig %s %s virtual:%d ID %u ICSR 0x%" PRIx64
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gicv5_activate(const char *domain, const char *type, bool virtual, uint32_t id) "GICv5 IRS Activate %s %s virtual:%d ID %u"
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+gicv5_deactivate(const char *domain, const char *type, bool virtual, uint32_t id) "GICv5 IRS Deactivate %s %s virtual:%d ID %u"
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gicv5_spi_state(uint32_t spi_id, bool level, bool pending, bool active) "GICv5 IRS SPI ID %u now level %d pending %d active %d"
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gicv5_irs_recalc_hppi_fail(const char *domain, uint32_t iaffid, const char *reason) "GICv5 IRS %s IAFFID %u: no HPPI: %s"
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gicv5_irs_recalc_hppi(const char *domain, uint32_t iaffid, uint32_t id, uint8_t prio) "GICv5 IRS %s IAFFID %u: new HPPI ID 0x%x prio %u"
include/hw/intc/arm_gicv5_stream.h
+14
@@ -211,4 +211,18 @@ void gicv5_forward_interrupt(ARMCPU *cpu, GICv5Domain domain);
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GICv5PendingIrq gicv5_get_hppi(GICv5Common *cs, GICv5Domain domain,
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uint32_t iaffid);
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+/**
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+ * gicv5_deactivate
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+ * @cs: GIC IRS to send command to
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+ * @id: interrupt ID
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+ * @domain: interrupt Domain to act on
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+ * @type: interrupt type (LPI or SPI)
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+ * @virtual: true if this is a virtual interrupt
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+ *
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+ * Deactivate the specified interrupt. There is no report back of
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+ * success/failure to the CPUIF in the protocol.
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+ */
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+void gicv5_deactivate(GICv5Common *cs, uint32_t id, GICv5Domain domain,
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+ GICv5IntType type, bool virtual);
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+
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#endif