target/riscv: Add the Zvfbfa extension implied rule
According to the Zvfbfa isa spec: The Zvfbfa extension requires the Zve32f and Zfbfmin extensions. Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Nutty Liu <nutty.liu@hotmail.com> Reviewed-by: Chao Liu <chao.liu.zevorn@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Max Chou <max.chou@sifive.com> Message-ID: <20260402125234.1371897-3-max.chou@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Max Chou committed
Apr 2, 2026 at 20:52 UTC
5c2792faa322a6b0c222cf6643672ff8447358d6
1 file changed
+11
-2
target/riscv/cpu.c
+11
-2
@@ -2622,6 +2622,15 @@ static RISCVCPUImpliedExtsRule SSCTR_IMPLIED = {
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},
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};
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+static RISCVCPUImpliedExtsRule ZVFBFA_IMPLIED = {
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+ .ext = CPU_CFG_OFFSET(ext_zvfbfa),
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+ .implied_multi_exts = {
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+ CPU_CFG_OFFSET(ext_zve32f), CPU_CFG_OFFSET(ext_zfbfmin),
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+
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+ RISCV_IMPLIED_EXTS_RULE_END
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+ },
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+};
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+
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RISCVCPUImpliedExtsRule *riscv_misa_ext_implied_rules[] = {
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&RVA_IMPLIED, &RVD_IMPLIED, &RVF_IMPLIED,
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&RVM_IMPLIED, &RVV_IMPLIED, NULL
@@ -2635,8 +2644,8 @@ RISCVCPUImpliedExtsRule *riscv_multi_ext_implied_rules[] = {
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&ZHINX_IMPLIED, &ZHINXMIN_IMPLIED, &ZICNTR_IMPLIED,
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&ZIHPM_IMPLIED, &ZK_IMPLIED, &ZKN_IMPLIED,
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&ZKS_IMPLIED, &ZVBB_IMPLIED, &ZVE32F_IMPLIED,
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- &ZVE32X_IMPLIED, &ZVE64D_IMPLIED, &ZVE64F_IMPLIED,
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- &ZVE64X_IMPLIED, &ZVFBFMIN_IMPLIED, &ZVFBFWMA_IMPLIED,
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+ &ZVE32X_IMPLIED, &ZVE64D_IMPLIED, &ZVE64F_IMPLIED, &ZVE64X_IMPLIED,
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+ &ZVFBFA_IMPLIED, &ZVFBFMIN_IMPLIED, &ZVFBFWMA_IMPLIED,
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&ZVFH_IMPLIED, &ZVFHMIN_IMPLIED, &ZVKN_IMPLIED,
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&ZVKNC_IMPLIED, &ZVKNG_IMPLIED, &ZVKNHB_IMPLIED,
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&ZVKS_IMPLIED, &ZVKSC_IMPLIED, &ZVKSG_IMPLIED, &SSCFG_IMPLIED,