@samitouri / QOSamiQemu / commits / 5dcc64828d

target/riscv: Use ELEN for Fractional LMUL check

The RISC-V spec states that """ For a given supported fractional LMUL setting, implementations must support SEW settings between SEWMIN and LMUL * ELEN, inclusive. """ We were previously checking VLEN, instead of ELEN, so let's update to check ELEN instead of VLEN for fractional scaling. Cc: qemu-stable@nongnu.org Resolves: https://gitlab.com/qemu-project/qemu/-/work_items/3196 Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Reviewed-by: Chao Liu <chao.liu.zevorn@gmail.com> Reviewed-by: Max Chou <max.chou@sifive.com> Message-ID: <20260415233740.3027321-5-alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>

Alistair Francis committed Apr 16, 2026 at 09:37 UTC 5dcc64828dc79c2426905db5fae885f6ccf93347

1 file changed +4 -5

target/riscv/vector_helper.c

+4 -5

@@ -70,18 +70,17 @@ target_ulong HELPER(vsetvl)(CPURISCVState *env, target_ulong s1,

70 bool ill_altfmt = true;

71 int xlen = riscv_cpu_xlen(env);

72 bool vill = (s2 >> (xlen - 1)) & 0x1;

73 - uint16_t vlen = cpu->cfg.vlenb << 3;

73 int8_t lmul;

75 if (vlmul & 4) {

76 /*

77 * Fractional LMUL, check:

78 *

80 - * VLEN * LMUL >= SEW

81 - * VLEN >> (8 - lmul) >= sew

82 - * (vlenb << 3) >> (8 - lmul) >= sew

79 + * ELEN * LMUL >= SEW

80 + * ELEN >> (8 - vlmul) >= sew

81 */

84 - if (vlmul == 4 || (vlen >> (8 - vlmul)) < sew) {

82 + if (vlmul == 4 ||

83 + (cpu->cfg.elen >> (8 - vlmul)) < sew) {

84 vill = true;

85 }

86 }