tcg/aarch64/tcg-target.c.inc: Manual replace of I3310, I3313
These are not formats in themselves, but extra constants to OR in with the existing ldst_imm format. Signed-off-by: Jim MacArthur <jim.macarthur@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20260402-aarch64-tcg-instruction-format-rename2-v1-2-0998a08a515c@linaro.org>
Jim MacArthur committed
Apr 2, 2026 at 15:20 UTC
5e3906dcfaa1427c6f890c85b4fce281dcb16531
1 file changed
+35
-29
tcg/aarch64/tcg-target.c.inc
+35
-29
@@ -458,8 +458,9 @@ typedef enum {
458
Ildst_imm_LDRVQ = 0x3c000000 | 3 << 22 | 0 << 30,
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Ildst_imm_STRVQ = 0x3c000000 | 2 << 22 | 0 << 30,
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- Ildst_imm_TO_I3310 = 0x00200800,
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- Ildst_imm_TO_I3313 = 0x01000000,
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+ /* Additions to the ldst_imm format */
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+ ldst_imm_to_reg = 0x00200800,
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+ ldst_imm_to_uimm = 0x01000000,
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/* Load/store register pair instructions. */
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Ildstpair_LDP = 0x28400000,
@@ -880,13 +881,13 @@ static void tcg_out_insn_qrr_e(TCGContext *s, AArch64Insn insn, bool q,
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| (rn & 0x1f) << 5 | (rd & 0x1f));
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}
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883
-static void tcg_out_insn_3310(TCGContext *s, AArch64Insn insn,
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- TCGReg rd, TCGReg base, TCGType ext,
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- TCGReg regoff)
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+static void tcg_out_insn_ldst_reg(TCGContext *s, AArch64Insn insn,
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+ TCGReg rd, TCGReg base, TCGType ext,
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+ TCGReg regoff)
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{
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/* Note the AArch64Insn constants above are for C3.3.12. Adjust. */
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- tcg_out32(s, insn | Ildst_imm_TO_I3310 | regoff << 16 |
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- 0x4000 | ext << 13 | base << 5 | (rd & 0x1f));
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+ tcg_out32(s, insn | ldst_imm_to_reg | regoff << 16 | 0x4000 | ext << 13 |
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+ base << 5 | (rd & 0x1f));
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}
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static void tcg_out_insn_ldst_imm(TCGContext *s, AArch64Insn insn,
@@ -895,11 +896,11 @@ static void tcg_out_insn_ldst_imm(TCGContext *s, AArch64Insn insn,
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tcg_out32(s, insn | (offset & 0x1ff) << 12 | rn << 5 | (rd & 0x1f));
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}
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-static void tcg_out_insn_3313(TCGContext *s, AArch64Insn insn,
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- TCGReg rd, TCGReg rn, uintptr_t scaled_uimm)
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+static void tcg_out_insn_ldst_uimm(TCGContext *s, AArch64Insn insn,
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+ TCGReg rd, TCGReg rn, uintptr_t scaled_uimm)
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{
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/* Note the AArch64Insn constants above are for C3.3.12. Adjust. */
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- tcg_out32(s, insn | Ildst_imm_TO_I3313 | scaled_uimm << 10
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+ tcg_out32(s, insn | ldst_imm_to_uimm | scaled_uimm << 10
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| rn << 5 | (rd & 0x1f));
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}
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@@ -1203,9 +1204,6 @@ static void tcg_out_addi_ptr(TCGContext *s, TCGReg rd, TCGReg rs,
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g_assert_not_reached();
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}
1206
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-/* Define something more legible for general use. */
1207
-#define tcg_out_ldst_r tcg_out_insn_3310
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-
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static void tcg_out_ldst(TCGContext *s, AArch64Insn insn, TCGReg rd,
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TCGReg rn, intptr_t offset, int lgsize)
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{
@@ -1214,7 +1212,7 @@ static void tcg_out_ldst(TCGContext *s, AArch64Insn insn, TCGReg rd,
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if (offset >= 0 && !(offset & ((1 << lgsize) - 1))) {
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uintptr_t scaled_uimm = offset >> lgsize;
1214
if (scaled_uimm <= 0xfff) {
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- tcg_out_insn_3313(s, insn, rd, rn, scaled_uimm);
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+ tcg_out_insn_ldst_uimm(s, insn, rd, rn, scaled_uimm);
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return;
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}
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}
@@ -1227,7 +1225,7 @@ static void tcg_out_ldst(TCGContext *s, AArch64Insn insn, TCGReg rd,
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/* Worst-case scenario, move offset to temp register, use reg offset. */
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tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_TMP0, offset);
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- tcg_out_ldst_r(s, insn, rd, rn, TCG_TYPE_I64, TCG_REG_TMP0);
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+ tcg_out_insn_ldst_reg(s, insn, rd, rn, TCG_TYPE_I64, TCG_REG_TMP0);
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}
1230
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static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg)
@@ -1764,28 +1762,32 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, MemOp memop, TCGType ext,
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{
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switch (memop & MO_SSIZE) {
1764
case MO_UB:
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- tcg_out_ldst_r(s, Ildst_imm_LDRB, data_r, h.base, h.index_ext, h.index);
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+ tcg_out_insn_ldst_reg(s, Ildst_imm_LDRB, data_r, h.base,
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+ h.index_ext, h.index);
1767
break;
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case MO_SB:
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- tcg_out_ldst_r(s, ext ? Ildst_imm_LDRSBX : Ildst_imm_LDRSBW,
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- data_r, h.base, h.index_ext, h.index);
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+ tcg_out_insn_ldst_reg(s, ext ? Ildst_imm_LDRSBX : Ildst_imm_LDRSBW,
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+ data_r, h.base, h.index_ext, h.index);
1771
break;
1772
case MO_UW:
1774
- tcg_out_ldst_r(s, Ildst_imm_LDRH, data_r, h.base, h.index_ext, h.index);
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+ tcg_out_insn_ldst_reg(s, Ildst_imm_LDRH, data_r, h.base, h.index_ext,
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+ h.index);
1775
break;
1776
case MO_SW:
1777
- tcg_out_ldst_r(s, (ext ? Ildst_imm_LDRSHX : Ildst_imm_LDRSHW),
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- data_r, h.base, h.index_ext, h.index);
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+ tcg_out_insn_ldst_reg(s, ext ? Ildst_imm_LDRSHX : Ildst_imm_LDRSHW,
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+ data_r, h.base, h.index_ext, h.index);
1779
break;
1780
case MO_UL:
1781
- tcg_out_ldst_r(s, Ildst_imm_LDRW, data_r, h.base, h.index_ext, h.index);
1781
+ tcg_out_insn_ldst_reg(s, Ildst_imm_LDRW, data_r, h.base, h.index_ext,
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+ h.index);
1783
break;
1784
case MO_SL:
1784
- tcg_out_ldst_r(s, Ildst_imm_LDRSWX, data_r, h.base, h.index_ext,
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- h.index);
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+ tcg_out_insn_ldst_reg(s, Ildst_imm_LDRSWX, data_r, h.base, h.index_ext,
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+ h.index);
1787
break;
1788
case MO_UQ:
1788
- tcg_out_ldst_r(s, Ildst_imm_LDRX, data_r, h.base, h.index_ext, h.index);
1789
+ tcg_out_insn_ldst_reg(s, Ildst_imm_LDRX, data_r, h.base, h.index_ext,
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+ h.index);
1791
break;
1792
default:
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g_assert_not_reached();
@@ -1797,16 +1799,20 @@ static void tcg_out_qemu_st_direct(TCGContext *s, MemOp memop,
1799
{
1800
switch (memop & MO_SIZE) {
1801
case MO_8:
1800
- tcg_out_ldst_r(s, Ildst_imm_STRB, data_r, h.base, h.index_ext, h.index);
1802
+ tcg_out_insn_ldst_reg(s, Ildst_imm_STRB, data_r, h.base,
1803
+ h.index_ext, h.index);
1804
break;
1805
case MO_16:
1803
- tcg_out_ldst_r(s, Ildst_imm_STRH, data_r, h.base, h.index_ext, h.index);
1806
+ tcg_out_insn_ldst_reg(s, Ildst_imm_STRH, data_r, h.base,
1807
+ h.index_ext, h.index);
1808
break;
1809
case MO_32:
1806
- tcg_out_ldst_r(s, Ildst_imm_STRW, data_r, h.base, h.index_ext, h.index);
1810
+ tcg_out_insn_ldst_reg(s, Ildst_imm_STRW, data_r, h.base,
1811
+ h.index_ext, h.index);
1812
break;
1813
case MO_64:
1809
- tcg_out_ldst_r(s, Ildst_imm_STRX, data_r, h.base, h.index_ext, h.index);
1814
+ tcg_out_insn_ldst_reg(s, Ildst_imm_STRX, data_r, h.base,
1815
+ h.index_ext, h.index);
1816
break;
1817
default:
1818
g_assert_not_reached();