@samitouri / QOSamiQemu / commits / 5e5a86bab8

hw/cxl: Add support for Maintenance command and Post Package Repair (PPR)

This adds initial support for the Maintenance command, specifically the soft and hard PPR operations on a dpa. The implementation allows to be executed at runtime, therefore semantically, data is retained and CXL.mem requests are correctly processed. Keep track of the requests upon a general media or DRAM event. Post Package Repair (PPR) maintenance operations may be supported by CXL devices that implement CXL.mem protocol. A PPR maintenance operation requests the CXL device to perform a repair operation on its media. For example, a CXL device with DRAM components that support PPR features may implement PPR Maintenance operations. DRAM components may support two types of PPR, hard PPR (hPPR), for a permanent row repair, and Soft PPR (sPPR), for a temporary row repair. Soft PPR is much faster than hPPR, but the repair is lost with a power cycle. CXL spec 3.2 section 8.2.10.7.1.2 describes the device's sPPR (soft PPR) maintenance operation and section 8.2.10.7.1.3 describes the device's hPPR (hard PPR) maintenance operation feature. CXL spec 3.2 section 8.2.10.7.2.1 describes the sPPR feature discovery and configuration. CXL spec 3.2 section 8.2.10.7.2.2 describes the hPPR feature discovery and configuration. CXL spec 3.2 section 8.2.10.2.1.4 Table 8-60 describes the Memory Sparing Event Record. Signed-off-by: Davidlohr Bueso <dave@stgolabs.net> Co-developed-by: Shiju Jose <shiju.jose@huawei.com> Signed-off-by: Shiju Jose <shiju.jose@huawei.com> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com> Message-Id: <20250917143330.294698-3-Jonathan.Cameron@huawei.com>

Davidlohr Bueso committed Sep 17, 2025 at 15:33 UTC 5e5a86bab8308a9d5db09cbfdf12cc3751dce0f7

4 files changed +517 -2

hw/cxl/cxl-mailbox-utils.c

+238 -2

@@ -86,6 +86,8 @@ enum {

86 #define GET_SUPPORTED 0x0

87 #define GET_FEATURE 0x1

88 #define SET_FEATURE 0x2

89 + MAINTENANCE = 0x06,

90 + #define PERFORM 0x0

91 IDENTIFY = 0x40,

92 #define MEMORY_DEVICE 0x0

93 CCLS = 0x41,

@@ -1111,8 +1113,8 @@ typedef struct CXLSupportedFeatureEntry {

1113 #define CXL_FEAT_ENTRY_ATTR_FLAG_CHANGABLE BIT(0)

1114 #define CXL_FEAT_ENTRY_ATTR_FLAG_DEEPEST_RESET_PERSISTENCE_MASK GENMASK(3, 1)

1115 #define CXL_FEAT_ENTRY_ATTR_FLAG_PERSIST_ACROSS_FIRMWARE_UPDATE BIT(4)

1114 -#define CXL_FEAT_ENTRY_ATTR_FLAG_SUPPORT_DEFAULT_SELECTION BIT(5)

1115 -#define CXL_FEAT_ENTRY_ATTR_FLAG_SUPPORT_SAVED_SELECTION BIT(6)

1116 +#define CXL_FEAT_ENTRY_ATTR_FLAG_SUPPORT_DEFAULT_SEL BIT(5)

1117 +#define CXL_FEAT_ENTRY_ATTR_FLAG_SUPPORT_SAVED_SEL BIT(6)

1118

1119 /* Supported Feature Entry : set feature effects */

1120 #define CXL_FEAT_ENTRY_SFE_CONFIG_CHANGE_COLD_RESET BIT(0)

@@ -1131,6 +1133,8 @@ typedef struct CXLSupportedFeatureEntry {

1133 enum CXL_SUPPORTED_FEATURES_LIST {

1134 CXL_FEATURE_PATROL_SCRUB = 0,

1135 CXL_FEATURE_ECS,

1136 + CXL_FEATURE_SPPR,

1137 + CXL_FEATURE_HPPR,

1138 CXL_FEATURE_MAX

1139 };

1140

@@ -1172,6 +1176,28 @@ enum CXL_SET_FEATURE_FLAG_DATA_TRANSFER {

1176 };

1177 #define CXL_SET_FEAT_DATA_SAVED_ACROSS_RESET BIT(3)

1178

1179 +/* CXL r3.2 section 8.2.10.7.2.1: sPPR Feature Discovery and Configuration */

1180 +static const QemuUUID soft_ppr_uuid = {

1181 + .data = UUID(0x892ba475, 0xfad8, 0x474e, 0x9d, 0x3e,

1182 + 0x69, 0x2c, 0x91, 0x75, 0x68, 0xbb)

1183 +};

1184 +

1185 +typedef struct CXLMemSoftPPRSetFeature {

1186 + CXLSetFeatureInHeader hdr;

1187 + CXLMemSoftPPRWriteAttrs feat_data;

1188 +} QEMU_PACKED QEMU_ALIGNED(16) CXLMemSoftPPRSetFeature;

1189 +

1190 +/* CXL r3.2 section 8.2.10.7.2.2: hPPR Feature Discovery and Configuration */

1191 +static const QemuUUID hard_ppr_uuid = {

1192 + .data = UUID(0x80ea4521, 0x786f, 0x4127, 0xaf, 0xb1,

1193 + 0xec, 0x74, 0x59, 0xfb, 0x0e, 0x24)

1194 +};

1195 +

1196 +typedef struct CXLMemHardPPRSetFeature {

1197 + CXLSetFeatureInHeader hdr;

1198 + CXLMemHardPPRWriteAttrs feat_data;

1199 +} QEMU_PACKED QEMU_ALIGNED(16) CXLMemHardPPRSetFeature;

1200 +

1201 /* CXL r3.1 section 8.2.9.9.11.1: Device Patrol Scrub Control Feature */

1202 static const QemuUUID patrol_scrub_uuid = {

1203 .data = UUID(0x96dad7d6, 0xfde8, 0x482b, 0xa7, 0x33,

@@ -1235,6 +1261,38 @@ static CXLRetCode cmd_features_get_supported(const struct cxl_cmd *cmd,

1261 for (entry = 0, index = get_feats_in->start_index;

1262 entry < req_entries; index++) {

1263 switch (index) {

1264 + case CXL_FEATURE_SPPR:

1265 + /* Fill supported feature entry for soft-PPR */

1266 + get_feats_out->feat_entries[entry++] =

1267 + (struct CXLSupportedFeatureEntry) {

1268 + .uuid = soft_ppr_uuid,

1269 + .feat_index = index,

1270 + .get_feat_size = sizeof(CXLMemSoftPPRReadAttrs),

1271 + .set_feat_size = sizeof(CXLMemSoftPPRWriteAttrs),

1272 + .attr_flags = CXL_FEAT_ENTRY_ATTR_FLAG_CHANGABLE |

1273 + CXL_FEAT_ENTRY_ATTR_FLAG_SUPPORT_DEFAULT_SEL,

1274 + .get_feat_version = CXL_MEMDEV_SPPR_GET_FEATURE_VERSION,

1275 + .set_feat_version = CXL_MEMDEV_SPPR_SET_FEATURE_VERSION,

1276 + .set_feat_effects = CXL_FEAT_ENTRY_SFE_IMMEDIATE_CONFIG_CHANGE |

1277 + CXL_FEAT_ENTRY_SFE_CEL_VALID,

1278 + };

1279 + break;

1280 + case CXL_FEATURE_HPPR:

1281 + /* Fill supported feature entry for hard-PPR */

1282 + get_feats_out->feat_entries[entry++] =

1283 + (struct CXLSupportedFeatureEntry) {

1284 + .uuid = hard_ppr_uuid,

1285 + .feat_index = index,

1286 + .get_feat_size = sizeof(CXLMemHardPPRReadAttrs),

1287 + .set_feat_size = sizeof(CXLMemHardPPRWriteAttrs),

1288 + .attr_flags = CXL_FEAT_ENTRY_ATTR_FLAG_CHANGABLE |

1289 + CXL_FEAT_ENTRY_ATTR_FLAG_SUPPORT_DEFAULT_SEL,

1290 + .get_feat_version = CXL_MEMDEV_HPPR_GET_FEATURE_VERSION,

1291 + .set_feat_version = CXL_MEMDEV_HPPR_SET_FEATURE_VERSION,

1292 + .set_feat_effects = CXL_FEAT_ENTRY_SFE_IMMEDIATE_CONFIG_CHANGE |

1293 + CXL_FEAT_ENTRY_SFE_CEL_VALID,

1294 + };

1295 + break;

1296 case CXL_FEATURE_PATROL_SCRUB:

1297 /* Fill supported feature entry for device patrol scrub control */

1298 get_feats_out->feat_entries[entry++] =

@@ -1333,6 +1391,26 @@ static CXLRetCode cmd_features_get_feature(const struct cxl_cmd *cmd,

1391 memcpy(payload_out,

1392 (uint8_t *)&ct3d->ecs_attrs + get_feature->offset,

1393 bytes_to_copy);

1394 + } else if (qemu_uuid_is_equal(&get_feature->uuid, &soft_ppr_uuid)) {

1395 + if (get_feature->offset >= sizeof(CXLMemSoftPPRReadAttrs)) {

1396 + return CXL_MBOX_INVALID_INPUT;

1397 + }

1398 + bytes_to_copy = sizeof(CXLMemSoftPPRReadAttrs) -

1399 + get_feature->offset;

1400 + bytes_to_copy = MIN(bytes_to_copy, get_feature->count);

1401 + memcpy(payload_out,

1402 + (uint8_t *)&ct3d->soft_ppr_attrs + get_feature->offset,

1403 + bytes_to_copy);

1404 + } else if (qemu_uuid_is_equal(&get_feature->uuid, &hard_ppr_uuid)) {

1405 + if (get_feature->offset >= sizeof(CXLMemHardPPRReadAttrs)) {

1406 + return CXL_MBOX_INVALID_INPUT;

1407 + }

1408 + bytes_to_copy = sizeof(CXLMemHardPPRReadAttrs) -

1409 + get_feature->offset;

1410 + bytes_to_copy = MIN(bytes_to_copy, get_feature->count);

1411 + memcpy(payload_out,

1412 + (uint8_t *)&ct3d->hard_ppr_attrs + get_feature->offset,

1413 + bytes_to_copy);

1414 } else {

1415 return CXL_MBOX_UNSUPPORTED;

1416 }

@@ -1444,6 +1522,44 @@ static CXLRetCode cmd_features_set_feature(const struct cxl_cmd *cmd,

1522 ct3d->ecs_wr_attrs.fru_attrs[count].ecs_config & 0x1F;

1523 }

1524 }

1525 + } else if (qemu_uuid_is_equal(&hdr->uuid, &soft_ppr_uuid)) {

1526 + CXLMemSoftPPRSetFeature *sppr_set_feature = (void *)payload_in;

1527 + CXLMemSoftPPRWriteAttrs *sppr_write_attrs =

1528 + &sppr_set_feature->feat_data;

1529 +

1530 + if (hdr->version != CXL_MEMDEV_SPPR_SET_FEATURE_VERSION) {

1531 + return CXL_MBOX_UNSUPPORTED;

1532 + }

1533 +

1534 + memcpy((uint8_t *)&ct3d->soft_ppr_wr_attrs + hdr->offset,

1535 + sppr_write_attrs, bytes_to_copy);

1536 + set_feat_info->data_size += bytes_to_copy;

1537 +

1538 + if (data_transfer_flag == CXL_SET_FEATURE_FLAG_FULL_DATA_TRANSFER ||

1539 + data_transfer_flag == CXL_SET_FEATURE_FLAG_FINISH_DATA_TRANSFER) {

1540 + ct3d->soft_ppr_attrs.op_mode = ct3d->soft_ppr_wr_attrs.op_mode;

1541 + ct3d->soft_ppr_attrs.sppr_op_mode =

1542 + ct3d->soft_ppr_wr_attrs.sppr_op_mode;

1543 + }

1544 + } else if (qemu_uuid_is_equal(&hdr->uuid, &hard_ppr_uuid)) {

1545 + CXLMemHardPPRSetFeature *hppr_set_feature = (void *)payload_in;

1546 + CXLMemHardPPRWriteAttrs *hppr_write_attrs =

1547 + &hppr_set_feature->feat_data;

1548 +

1549 + if (hdr->version != CXL_MEMDEV_HPPR_SET_FEATURE_VERSION) {

1550 + return CXL_MBOX_UNSUPPORTED;

1551 + }

1552 +

1553 + memcpy((uint8_t *)&ct3d->hard_ppr_wr_attrs + hdr->offset,

1554 + hppr_write_attrs, bytes_to_copy);

1555 + set_feat_info->data_size += bytes_to_copy;

1556 +

1557 + if (data_transfer_flag == CXL_SET_FEATURE_FLAG_FULL_DATA_TRANSFER ||

1558 + data_transfer_flag == CXL_SET_FEATURE_FLAG_FINISH_DATA_TRANSFER) {

1559 + ct3d->hard_ppr_attrs.op_mode = ct3d->hard_ppr_wr_attrs.op_mode;

1560 + ct3d->hard_ppr_attrs.hppr_op_mode =

1561 + ct3d->hard_ppr_wr_attrs.hppr_op_mode;

1562 + }

1563 } else {

1564 return CXL_MBOX_UNSUPPORTED;

1565 }

@@ -1456,6 +1572,10 @@ static CXLRetCode cmd_features_set_feature(const struct cxl_cmd *cmd,

1572 memset(&ct3d->patrol_scrub_wr_attrs, 0, set_feat_info->data_size);

1573 } else if (qemu_uuid_is_equal(&hdr->uuid, &ecs_uuid)) {

1574 memset(&ct3d->ecs_wr_attrs, 0, set_feat_info->data_size);

1575 + } else if (qemu_uuid_is_equal(&hdr->uuid, &soft_ppr_uuid)) {

1576 + memset(&ct3d->soft_ppr_wr_attrs, 0, set_feat_info->data_size);

1577 + } else if (qemu_uuid_is_equal(&hdr->uuid, &hard_ppr_uuid)) {

1578 + memset(&ct3d->hard_ppr_wr_attrs, 0, set_feat_info->data_size);

1579 }

1580 set_feat_info->data_transfer_flag = 0;

1581 set_feat_info->data_saved_across_reset = false;

@@ -1466,6 +1586,116 @@ static CXLRetCode cmd_features_set_feature(const struct cxl_cmd *cmd,

1586 return CXL_MBOX_SUCCESS;

1587 }

1588

1589 +static void cxl_mbox_create_mem_sparing_event_records(CXLType3Dev *ct3d,

1590 + uint8_t maint_op_class, uint8_t maint_op_sub_class,

1591 + CXLMaintenance *ent)

1592 +{

1593 + CXLEventSparing event_rec = {};

1594 +

1595 + cxl_assign_event_header(&event_rec.hdr,

1596 + &sparing_uuid,

1597 + (1 << CXL_EVENT_TYPE_INFO),

1598 + sizeof(event_rec),

1599 + cxl_device_get_timestamp(&ct3d->cxl_dstate),

1600 + 1, maint_op_class, 1, maint_op_sub_class,

1601 + 0, 0, 0, 0);

1602 + if (ent) {

1603 + event_rec.flags = 0;

1604 + event_rec.result = 0;

1605 + stw_le_p(&event_rec.res_avail, 2);

1606 + stw_le_p(&event_rec.validity_flags, ent->validity_flags);

1607 + event_rec.channel = ent->channel;

1608 + event_rec.rank = ent->rank;

1609 + st24_le_p(event_rec.nibble_mask, ent->nibble_mask);

1610 + event_rec.bank_group = ent->bank_group;

1611 + event_rec.bank = ent->bank;

1612 + st24_le_p(event_rec.row, ent->row);

1613 + stw_le_p(&event_rec.column, ent->column);

1614 + event_rec.sub_channel = ent->sub_channel;

1615 + if (ent->validity_flags & CXL_MSER_VALID_COMP_ID) {

1616 + strncpy((char *)event_rec.component_id, (char *)ent->component_id,

1617 + sizeof(event_rec.component_id));

1618 + }

1619 + } else {

1620 + return;

1621 + }

1622 +

1623 + if (cxl_event_insert(&ct3d->cxl_dstate,

1624 + CXL_EVENT_TYPE_INFO,

1625 + (CXLEventRecordRaw *)&event_rec)) {

1626 + cxl_event_irq_assert(ct3d);

1627 + }

1628 +}

1629 +

1630 +

1631 +static void cxl_perform_ppr(CXLType3Dev *ct3d, uint64_t dpa)

1632 +{

1633 + CXLMaintenance *ent, *next;

1634 +

1635 + QLIST_FOREACH_SAFE(ent, &ct3d->maint_list, node, next) {

1636 + if (dpa == ent->dpa) {

1637 + /* Produce a Memory Sparing Event Record */

1638 + if (ct3d->soft_ppr_attrs.sppr_op_mode &

1639 + CXL_MEMDEV_SPPR_OP_MODE_MEM_SPARING_EV_REC_EN) {

1640 + cxl_mbox_create_mem_sparing_event_records(ct3d,

1641 + CXL_MEMDEV_MAINT_CLASS_SPARING,

1642 + CXL_MEMDEV_MAINT_SUBCLASS_CACHELINE_SPARING,

1643 + ent);

1644 + }

1645 + break;

1646 + }

1647 + }

1648 +}

1649 +

1650 +/* CXL r3.2 section 8.2.10.7.1 - Perform Maintenance (Opcode 0600h) */

1651 +#define MAINTENANCE_PPR_QUERY_RESOURCES BIT(0)

1652 +

1653 +static CXLRetCode cmd_media_perform_maintenance(const struct cxl_cmd *cmd,

1654 + uint8_t *payload_in, size_t len_in,

1655 + uint8_t *payload_out, size_t *len_out,

1656 + CXLCCI *cci)

1657 +{

1658 + struct {

1659 + uint8_t class;

1660 + uint8_t subclass;

1661 + union {

1662 + struct {

1663 + uint8_t flags;

1664 + uint64_t dpa;

1665 + uint8_t nibble_mask[3];

1666 + } QEMU_PACKED ppr;

1667 + };

1668 + } QEMU_PACKED *maint_in = (void *)payload_in;

1669 + CXLType3Dev *ct3d = CXL_TYPE3(cci->d);

1670 +

1671 + if (maintenance_running(cci)) {

1672 + return CXL_MBOX_BUSY;

1673 + }

1674 +

1675 + switch (maint_in->class) {

1676 + case CXL_MEMDEV_MAINT_CLASS_NO_OP:

1677 + return CXL_MBOX_SUCCESS; /* nop */

1678 + case CXL_MEMDEV_MAINT_CLASS_PPR:

1679 + if (maint_in->ppr.flags & MAINTENANCE_PPR_QUERY_RESOURCES) {

1680 + return CXL_MBOX_SUCCESS;

1681 + }

1682 +

1683 + switch (maint_in->subclass) {

1684 + case CXL_MEMDEV_MAINT_SUBCLASS_SPPR:

1685 + case CXL_MEMDEV_MAINT_SUBCLASS_HPPR:

1686 + cxl_perform_ppr(ct3d, ldq_le_p(&maint_in->ppr.dpa));

1687 + return CXL_MBOX_SUCCESS;

1688 + default:

1689 + return CXL_MBOX_INVALID_INPUT;

1690 + }

1691 + break;

1692 + default:

1693 + return CXL_MBOX_INVALID_INPUT;

1694 + }

1695 +

1696 + return CXL_MBOX_SUCCESS;

1697 +}

1698 +

1699 /* CXL r3.1 Section 8.2.9.9.1.1: Identify Memory Device (Opcode 4000h) */

1700 static CXLRetCode cmd_identify_memory_device(const struct cxl_cmd *cmd,

1701 uint8_t *payload_in,

@@ -3767,6 +3997,12 @@ static const struct cxl_cmd cxl_cmd_set[256][256] = {

3997 CXL_MBOX_IMMEDIATE_POLICY_CHANGE |

3998 CXL_MBOX_IMMEDIATE_LOG_CHANGE |

3999 CXL_MBOX_SECURITY_STATE_CHANGE)},

4000 + [MAINTENANCE][PERFORM] = { "MAINTENANCE_PERFORM",

4001 + cmd_media_perform_maintenance, ~0,

4002 + CXL_MBOX_IMMEDIATE_CONFIG_CHANGE |

4003 + CXL_MBOX_IMMEDIATE_DATA_CHANGE |

4004 + CXL_MBOX_IMMEDIATE_LOG_CHANGE |

4005 + CXL_MBOX_BACKGROUND_OPERATION },

4006 [IDENTIFY][MEMORY_DEVICE] = { "IDENTIFY_MEMORY_DEVICE",

4007 cmd_identify_memory_device, 0, 0 },

4008 [CCLS][GET_PARTITION_INFO] = { "CCLS_GET_PARTITION_INFO",

hw/mem/cxl_type3.c

+125

@@ -964,6 +964,32 @@ static void ct3_realize(PCIDevice *pci_dev, Error **errp)

964 ct3d->ecs_attrs.fru_attrs[count].ecs_flags = 0;

965 }

966

967 + /* Set default values for soft-PPR attributes */

968 + ct3d->soft_ppr_attrs = (CXLMemSoftPPRReadAttrs) {

969 + .max_maint_latency = 0x5, /* 100 ms */

970 + .op_caps = 0, /* require host involvement */

971 + .op_mode = 0,

972 + .maint_op_class = CXL_MEMDEV_MAINT_CLASS_PPR,

973 + .maint_op_subclass = CXL_MEMDEV_MAINT_SUBCLASS_SPPR,

974 + .sppr_flags = CXL_MEMDEV_SPPR_DPA_SUPPORT_FLAG |

975 + CXL_MEMDEV_SPPR_MEM_SPARING_EV_REC_CAP_FLAG,

976 + .restriction_flags = 0,

977 + .sppr_op_mode = CXL_MEMDEV_SPPR_OP_MODE_MEM_SPARING_EV_REC_EN

978 + };

979 +

980 + /* Set default value for hard-PPR attributes */

981 + ct3d->hard_ppr_attrs = (CXLMemHardPPRReadAttrs) {

982 + .max_maint_latency = 0x5, /* 100 ms */

983 + .op_caps = 0, /* require host involvement */

984 + .op_mode = 0,

985 + .maint_op_class = CXL_MEMDEV_MAINT_CLASS_PPR,

986 + .maint_op_subclass = CXL_MEMDEV_MAINT_SUBCLASS_HPPR,

987 + .hppr_flags = CXL_MEMDEV_HPPR_DPA_SUPPORT_FLAG |

988 + CXL_MEMDEV_HPPR_MEM_SPARING_EV_REC_CAP_FLAG,

989 + .restriction_flags = 0,

990 + .hppr_op_mode = CXL_MEMDEV_HPPR_OP_MODE_MEM_SPARING_EV_REC_EN

991 + };

992 +

993 return;

994

995 err_release_cdat:

@@ -1667,6 +1693,75 @@ static int ct3d_qmp_cxl_event_log_enc(CxlEventLog log)

1693 return -EINVAL;

1694 }

1695 }

1696 +

1697 +static void cxl_maintenance_insert(CXLType3Dev *ct3d, uint64_t dpa,

1698 + bool has_channel, uint8_t channel,

1699 + bool has_rank, uint8_t rank,

1700 + bool has_nibble_mask, uint32_t nibble_mask,

1701 + bool has_bank_group, uint8_t bank_group,

1702 + bool has_bank, uint8_t bank,

1703 + bool has_row, uint32_t row,

1704 + bool has_column, uint16_t column,

1705 + const char *component_id,

1706 + bool has_comp_id_pldm, bool is_comp_id_pldm,

1707 + bool has_sub_channel, uint8_t sub_channel)

1708 +{

1709 + CXLMaintenance *ent, *m;

1710 +

1711 + QLIST_FOREACH(ent, &ct3d->maint_list, node) {

1712 + if (dpa == ent->dpa) {

1713 + return;

1714 + }

1715 + }

1716 + m = g_new0(CXLMaintenance, 1);

1717 + memset(m, 0, sizeof(*m));

1718 + m->dpa = dpa;

1719 + m->validity_flags = 0;

1720 +

1721 + if (has_channel) {

1722 + m->channel = channel;

1723 + m->validity_flags |= CXL_MSER_VALID_CHANNEL;

1724 + }

1725 + if (has_rank) {

1726 + m->rank = rank;

1727 + m->validity_flags |= CXL_MSER_VALID_RANK;

1728 + }

1729 + if (has_nibble_mask) {

1730 + m->nibble_mask = nibble_mask;

1731 + m->validity_flags |= CXL_MSER_VALID_NIB_MASK;

1732 + }

1733 + if (has_bank_group) {

1734 + m->bank_group = bank_group;

1735 + m->validity_flags |= CXL_MSER_VALID_BANK_GROUP;

1736 + }

1737 + if (has_bank) {

1738 + m->bank = bank;

1739 + m->validity_flags |= CXL_MSER_VALID_BANK;

1740 + }

1741 + if (has_row) {

1742 + m->row = row;

1743 + m->validity_flags |= CXL_MSER_VALID_ROW;

1744 + }

1745 + if (has_column) {

1746 + m->column = column;

1747 + m->validity_flags |= CXL_MSER_VALID_COLUMN;

1748 + }

1749 + if (has_sub_channel) {

1750 + m->sub_channel = sub_channel;

1751 + m->validity_flags |= CXL_MSER_VALID_SUB_CHANNEL;

1752 + }

1753 + if (component_id) {

1754 + strncpy((char *)m->component_id, component_id,

1755 + sizeof(m->component_id) - 1);

1756 + m->validity_flags |= CXL_MSER_VALID_COMP_ID;

1757 + if (has_comp_id_pldm && is_comp_id_pldm) {

1758 + m->validity_flags |= CXL_MSER_VALID_COMP_ID_FORMAT;

1759 + }

1760 + }

1761 +

1762 + QLIST_INSERT_HEAD(&ct3d->maint_list, m, node);

1763 +}

1764 +

1765 /* Component ID is device specific. Define this as a string. */

1766 void qmp_cxl_inject_general_media_event(const char *path, CxlEventLog log,

1767 uint32_t flags, bool has_maint_op_class,

@@ -1715,6 +1810,11 @@ void qmp_cxl_inject_general_media_event(const char *path, CxlEventLog log,

1810 error_setg(errp, "Unhandled error log type");

1811 return;

1812 }

1813 + if (rc == CXL_EVENT_TYPE_INFO &&

1814 + (flags & CXL_EVENT_REC_FLAGS_MAINT_NEEDED)) {

1815 + error_setg(errp, "Informational event cannot require maintenance");

1816 + return;

1817 + }

1818 enc_log = rc;

1819

1820 memset(&gem, 0, sizeof(gem));

@@ -1773,6 +1873,15 @@ void qmp_cxl_inject_general_media_event(const char *path, CxlEventLog log,

1873 if (cxl_event_insert(cxlds, enc_log, (CXLEventRecordRaw *)&gem)) {

1874 cxl_event_irq_assert(ct3d);

1875 }

1876 +

1877 + if (flags & CXL_EVENT_REC_FLAGS_MAINT_NEEDED) {

1878 + cxl_maintenance_insert(ct3d, dpa, has_channel, channel,

1879 + has_rank, rank,

1880 + 0, 0, 0, 0, 0, 0, 0, 0,

1881 + 0, 0, component_id,

1882 + has_comp_id_pldm, is_comp_id_pldm,

1883 + 0, 0);

1884 + }

1885 }

1886

1887 #define CXL_DRAM_VALID_CHANNEL BIT(0)

@@ -1842,6 +1951,11 @@ void qmp_cxl_inject_dram_event(const char *path, CxlEventLog log,

1951 error_setg(errp, "Unhandled error log type");

1952 return;

1953 }

1954 + if (rc == CXL_EVENT_TYPE_INFO &&

1955 + (flags & CXL_EVENT_REC_FLAGS_MAINT_NEEDED)) {

1956 + error_setg(errp, "Informational event cannot require maintenance");

1957 + return;

1958 + }

1959 enc_log = rc;

1960

1961 memset(&dram, 0, sizeof(dram));

@@ -1935,6 +2049,17 @@ void qmp_cxl_inject_dram_event(const char *path, CxlEventLog log,

2049 if (cxl_event_insert(cxlds, enc_log, (CXLEventRecordRaw *)&dram)) {

2050 cxl_event_irq_assert(ct3d);

2051 }

2052 +

2053 + if (flags & CXL_EVENT_REC_FLAGS_MAINT_NEEDED) {

2054 + cxl_maintenance_insert(ct3d, dpa, has_channel, channel,

2055 + has_rank, rank,

2056 + has_nibble_mask, nibble_mask,

2057 + has_bank_group, bank_group,

2058 + has_bank, bank, has_row, row,

2059 + has_column, column, component_id,

2060 + has_comp_id_pldm, is_comp_id_pldm,

2061 + has_sub_channel, sub_channel);

2062 + }

2063 }

2064

2065 #define CXL_MMER_VALID_COMPONENT BIT(0)

include/hw/cxl/cxl_device.h

+112

@@ -430,6 +430,12 @@ static inline bool cxl_dev_media_disabled(CXLDeviceState *cxl_dstate)

430 uint64_t dev_status_reg = cxl_dstate->mbox_reg_state64[R_CXL_MEM_DEV_STS];

431 return FIELD_EX64(dev_status_reg, CXL_MEM_DEV_STS, MEDIA_STATUS) == 0x3;

432 }

433 +

434 +static inline bool maintenance_running(CXLCCI *cci)

435 +{

436 + return cci->bg.runtime && cci->bg.opcode == 0x0600;

437 +}

438 +

439 static inline bool scan_media_running(CXLCCI *cci)

440 {

441 return !!cci->bg.runtime && cci->bg.opcode == 0x4304;

@@ -443,6 +449,23 @@ typedef struct CXLError {

449

450 typedef QTAILQ_HEAD(, CXLError) CXLErrorList;

451

452 +typedef struct CXLMaintenance {

453 + uint64_t dpa;

454 + uint16_t validity_flags;

455 + uint8_t channel;

456 + uint8_t rank;

457 + uint32_t nibble_mask;

458 + uint8_t bank_group;

459 + uint8_t bank;

460 + uint32_t row;

461 + uint16_t column;

462 + uint8_t component_id[CXL_EVENT_GEN_MED_COMP_ID_SIZE];

463 + uint8_t sub_channel;

464 + QLIST_ENTRY(CXLMaintenance) node;

465 +} CXLMaintenance;

466 +

467 +typedef QLIST_HEAD(, CXLMaintenance) CXLMaintenanceList;

468 +

469 typedef struct CXLPoison {

470 uint64_t start, length;

471 uint8_t type;

@@ -455,6 +478,87 @@ typedef struct CXLPoison {

478 typedef QLIST_HEAD(, CXLPoison) CXLPoisonList;

479 #define CXL_POISON_LIST_LIMIT 256

480

481 +/* CXL memory maintenance operation */

482 +/*

483 + * CXL r3.2 section 8.2.10.7.2, Table 8-125: Mainteance Operation:

484 + * Classes, Subclasses, and Feature UUIDs

485 + */

486 +#define CXL_MEMDEV_MAINT_CLASS_NO_OP 0x0

487 +#define CXL_MEMDEV_MAINT_CLASS_PPR 0x1

488 +#define CXL_MEMDEV_MAINT_CLASS_SPARING 0x2

489 +#define CXL_MEMDEV_MAINT_CLASS_DEV_BUILT_IN_TEST 0x3

490 +

491 +#define CXL_MEMDEV_MAINT_SUBCLASS_SPPR 0x0

492 +#define CXL_MEMDEV_MAINT_SUBCLASS_HPPR 0x1

493 +

494 +#define CXL_MEMDEV_MAINT_SUBCLASS_CACHELINE_SPARING 0x0

495 +#define CXL_MEMDEV_MAINT_SUBCLASS_ROW_SPARING 0x1

496 +#define CXL_MEMDEV_MAINT_SUBCLASS_BANK_SPARING 0x2

497 +#define CXL_MEMDEV_MAINT_SUBCLASS_RANK_SPARING 0x3

498 +

499 +/* CXL memory Post Package Repair control attributes */

500 +/*

501 + * CXL r3.2 section 8.2.10.7.2.1, Table 8-128 and 8-129:

502 + * sPPR Feature Readable/Writable Attributes

503 + */

504 +typedef struct CXLMemSoftPPRReadAttrs {

505 + uint8_t max_maint_latency;

506 + uint16_t op_caps;

507 + uint16_t op_mode;

508 + uint8_t maint_op_class;

509 + uint8_t maint_op_subclass;

510 + uint8_t rsvd[9];

511 + uint8_t sppr_flags;

512 + uint16_t restriction_flags;

513 + uint8_t sppr_op_mode;

514 +} QEMU_PACKED CXLMemSoftPPRReadAttrs;

515 +

516 +typedef struct CXLMemSoftPPRWriteAttrs {

517 + uint16_t op_mode;

518 + uint8_t sppr_op_mode;

519 +} QEMU_PACKED CXLMemSoftPPRWriteAttrs;

520 +

521 +#define CXL_MEMDEV_SPPR_GET_FEATURE_VERSION 0x03

522 +#define CXL_MEMDEV_SPPR_SET_FEATURE_VERSION 0x03

523 +#define CXL_MEMDEV_SPPR_DPA_SUPPORT_FLAG BIT(0)

524 +#define CXL_MEMDEV_SPPR_NIBBLE_SUPPORT_FLAG BIT(1)

525 +#define CXL_MEMDEV_SPPR_MEM_SPARING_EV_REC_CAP_FLAG BIT(2)

526 +#define CXL_MEMDEV_SPPR_DEV_INITIATED_AT_BOOT_CAP_FLAG BIT(3)

527 +

528 +#define CXL_MEMDEV_SPPR_OP_MODE_MEM_SPARING_EV_REC_EN BIT(0)

529 +#define CXL_MEMDEV_SPPR_OP_MODE_DEV_INITIATED_AT_BOOT BIT(1)

530 +

531 +/*

532 + * CXL r3.2 section 8.2.10.7.2.2, Table 8-131 and 8-132:

533 + * hPPR Feature Readable/Writable Attributes

534 + */

535 +typedef struct CXLMemHardPPRReadAttrs {

536 + uint8_t max_maint_latency;

537 + uint16_t op_caps;

538 + uint16_t op_mode;

539 + uint8_t maint_op_class;

540 + uint8_t maint_op_subclass;

541 + uint8_t rsvd[9];

542 + uint8_t hppr_flags;

543 + uint16_t restriction_flags;

544 + uint8_t hppr_op_mode;

545 +} QEMU_PACKED CXLMemHardPPRReadAttrs;

546 +

547 +typedef struct CXLMemHardPPRWriteAttrs {

548 + uint16_t op_mode;

549 + uint8_t hppr_op_mode;

550 +} QEMU_PACKED CXLMemHardPPRWriteAttrs;

551 +

552 +#define CXL_MEMDEV_HPPR_GET_FEATURE_VERSION 0x03

553 +#define CXL_MEMDEV_HPPR_SET_FEATURE_VERSION 0x03

554 +#define CXL_MEMDEV_HPPR_DPA_SUPPORT_FLAG BIT(0)

555 +#define CXL_MEMDEV_HPPR_NIBBLE_SUPPORT_FLAG BIT(1)

556 +#define CXL_MEMDEV_HPPR_MEM_SPARING_EV_REC_CAP_FLAG BIT(2)

557 +#define CXL_MEMDEV_HPPR_DEV_INITIATED_AT_BOOT_CAP_FLAG BIT(3)

558 +

559 +#define CXL_MEMDEV_HPPR_OP_MODE_MEM_SPARING_EV_REC_EN BIT(0)

560 +#define CXL_MEMDEV_HPPR_OP_MODE_DEV_INITIATED_AT_BOOT BIT(1)

561 +

562 /* CXL memory device patrol scrub control attributes */

563 typedef struct CXLMemPatrolScrubReadAttrs {

564 uint8_t scrub_cycle_cap;

@@ -605,6 +709,9 @@ struct CXLType3Dev {

709 /* Error injection */

710 CXLErrorList error_list;

711

712 + /* Keep track of maintenance requests */

713 + CXLMaintenanceList maint_list;

714 +

715 /* Poison Injection - cache */

716 CXLPoisonList poison_list;

717 unsigned int poison_list_cnt;

@@ -617,6 +724,11 @@ struct CXLType3Dev {

724

725 CXLSetFeatureInfo set_feat_info;

726

727 + /* PPR control attributes */

728 + CXLMemSoftPPRReadAttrs soft_ppr_attrs;

729 + CXLMemSoftPPRWriteAttrs soft_ppr_wr_attrs;

730 + CXLMemHardPPRReadAttrs hard_ppr_attrs;

731 + CXLMemHardPPRWriteAttrs hard_ppr_wr_attrs;

732 /* Patrol scrub control attributes */

733 CXLMemPatrolScrubReadAttrs patrol_scrub_attrs;

734 CXLMemPatrolScrubWriteAttrs patrol_scrub_wr_attrs;

include/hw/cxl/cxl_events.h

+42

@@ -219,4 +219,46 @@ typedef enum CXLDCEventType {

219 DC_EVENT_CAPACITY_RELEASED = 0x5,

220 } CXLDCEventType;

221

222 +/*

223 + * CXL r3.2 section Table 8-60: Memory Sparing Event Record

224 + * All fields little endian.

225 + */

226 +#define CXL_MSER_VALID_CHANNEL BIT(0)

227 +#define CXL_MSER_VALID_RANK BIT(1)

228 +#define CXL_MSER_VALID_NIB_MASK BIT(2)

229 +#define CXL_MSER_VALID_BANK_GROUP BIT(3)

230 +#define CXL_MSER_VALID_BANK BIT(4)

231 +#define CXL_MSER_VALID_ROW BIT(5)

232 +#define CXL_MSER_VALID_COLUMN BIT(6)

233 +#define CXL_MSER_VALID_COMP_ID BIT(7)

234 +#define CXL_MSER_VALID_COMP_ID_FORMAT BIT(8)

235 +#define CXL_MSER_VALID_SUB_CHANNEL BIT(9)

236 +

237 +typedef struct CXLEventSparing {

238 + CXLEventRecordHdr hdr;

239 + uint8_t maint_op_class;

240 + uint8_t maint_op_subclass;

241 + uint8_t flags;

242 + uint8_t result;

243 + uint16_t validity_flags;

244 + uint8_t reserved1[6];

245 + uint16_t res_avail;

246 + uint8_t channel;

247 + uint8_t rank;

248 + uint8_t nibble_mask[3];

249 + uint8_t bank_group;

250 + uint8_t bank;

251 + uint8_t row[3];

252 + uint16_t column;

253 + uint8_t component_id[CXL_EVENT_GEN_MED_COMP_ID_SIZE];

254 + uint8_t sub_channel;

255 + uint8_t reserved2[0x25];

256 +} QEMU_PACKED CXLEventSparing;

257 +

258 +/* CXL r3.2 Table 8-60: Memory Sparing Event Record */

259 +static const QemuUUID sparing_uuid = {

260 + .data = UUID(0xe71f3a40, 0x2d29, 0x4092, 0x8a, 0x39,

261 + 0x4d, 0x1c, 0x96, 0x6c, 0x7c, 0x65),

262 +};

263 +

264 #endif /* CXL_EVENTS_H */