target/riscv: Update MISA.X for non-standard extensions
MISA.X is set if there are any non-standard extensions. We should set MISA.X when any of the vendor extensions is enabled. Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Max Chou <max.chou@sifive.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20260424050509.3935180-3-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Frank Chang committed
Apr 24, 2026 at 13:05 UTC
613bb1949fffc4aeb9e554e35fecc7d6f7ddd27b
2 files changed
+16
target/riscv/cpu.h
+1
@@ -69,6 +69,7 @@ typedef struct CPUArchState CPURISCVState;
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#define RVH RV('H')
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#define RVG RV('G')
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#define RVB RV('B')
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+#define RVX RV('X')
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extern const uint32_t misa_bits[];
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const char *riscv_get_misa_ext_name(uint32_t bit);
target/riscv/tcg/tcg-cpu.c
+15
@@ -1201,6 +1201,20 @@ static void riscv_cpu_update_misa_c(RISCVCPU *cpu)
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}
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}
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+/* MISA.X is set when any of the non-standard extensions is enabled. */
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+static void riscv_cpu_update_misa_x(RISCVCPU *cpu)
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+{
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+ CPURISCVState *env = &cpu->env;
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+ const RISCVCPUMultiExtConfig *arr = riscv_cpu_vendor_exts;
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+
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+ for (int i = 0; arr[i].name != NULL; i++) {
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+ if (isa_ext_is_enabled(cpu, arr[i].offset)) {
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+ riscv_cpu_set_misa_ext(env, env->misa_ext | RVX);
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+ break;
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+ }
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+ }
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+}
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+
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void riscv_tcg_cpu_finalize_features(RISCVCPU *cpu, Error **errp)
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{
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CPURISCVState *env = &cpu->env;
@@ -1209,6 +1223,7 @@ void riscv_tcg_cpu_finalize_features(RISCVCPU *cpu, Error **errp)
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riscv_cpu_init_implied_exts_rules();
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riscv_cpu_enable_implied_rules(cpu);
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riscv_cpu_update_misa_c(cpu);
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+ riscv_cpu_update_misa_x(cpu);
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riscv_cpu_validate_misa_priv(env, &local_err);
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if (local_err != NULL) {