target/mips: split Octeon SEQI/SNEI decode
Decode the equality and inequality forms as explicit SEQI/SNEI instructions rather than using shared generated SEQNEI entries. The explicit decoder names match the architectural mnemonics, which makes the translator entry points and trace/debug output easier to correlate with the instruction set. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: James Hilliard <james.hilliard1@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> [PMD: Split SEQNE vs SEQNEI (this patch)] Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20260520172313.23777-10-philmd@linaro.org>
James Hilliard committed
Apr 21, 2026 at 11:27 UTC
638e8e64fd53abf890e4bc3b208e1b3fab1f005b
2 files changed
+16
-15
target/mips/tcg/octeon.decode
+3
-1
@@ -30,6 +30,7 @@ BBIT 11 set:1 . 10 rs:5 ..... offset:s16 p=%bbit_p
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# SNEI rt, rs, immediate
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@r3 ...... rs:5 rt:5 rd:5 ..... ......
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+&cmpi rs rt imm
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%bitfield_p 0:1 6:5
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@bitfield ...... rs:5 rt:5 lenm1:5 ..... ..... . p=%bitfield_p
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@@ -40,7 +41,8 @@ CINS 011100 ..... ..... ..... ..... 11001 . @bitfield
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POP 011100 rs:5 00000 rd:5 00000 10110 dw:1
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SEQ 011100 ..... ..... ..... 00000 101010 @r3
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SNE 011100 ..... ..... ..... 00000 101011 @r3
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-SEQNEI 011100 rs:5 rt:5 imm:s10 10111 ne:1
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+SEQI 011100 rs:5 rt:5 imm:s10 101110 &cmpi
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+SNEI 011100 rs:5 rt:5 imm:s10 101111 &cmpi
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&lx base index rd
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@lx ...... base:5 index:5 rd:5 ...... ..... &lx
target/mips/tcg/octeon_translate.c
+13
-14
@@ -132,29 +132,28 @@ static bool trans_SNE(DisasContext *ctx, arg_SNE *a)
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return do_seq_sne(ctx, a, TCG_COND_NE);
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}
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-static bool trans_SEQNEI(DisasContext *ctx, arg_SEQNEI *a)
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+static bool do_seqi_snei(DisasContext *ctx, const arg_cmpi *a, TCGCond cond)
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{
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TCGv_i64 t0;
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- if (a->rt == 0) {
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- /* nop */
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- return true;
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- }
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-
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t0 = tcg_temp_new_i64();
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-
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gen_load_gpr(t0, a->rs);
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- /* Sign-extend to 64 bit value */
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- target_ulong imm = a->imm;
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- if (a->ne) {
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- tcg_gen_setcondi_i64(TCG_COND_NE, cpu_gpr[a->rt], t0, imm);
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- } else {
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- tcg_gen_setcondi_i64(TCG_COND_EQ, cpu_gpr[a->rt], t0, imm);
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- }
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+ tcg_gen_setcondi_i64(cond, t0, t0, a->imm);
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+ gen_store_gpr(t0, a->rt);
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return true;
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}
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+static bool trans_SEQI(DisasContext *ctx, arg_SEQI *a)
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+{
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+ return do_seqi_snei(ctx, a, TCG_COND_EQ);
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+}
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+
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+static bool trans_SNEI(DisasContext *ctx, arg_SNEI *a)
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+{
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+ return do_seqi_snei(ctx, a, TCG_COND_NE);
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+}
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+
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static bool trans_lx(DisasContext *ctx, arg_lx *a, MemOp mop)
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{
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gen_lx(ctx, a->rd, a->base, a->index, mop);