target/arm: migrate FP/SIMD trap syndromes to registerfields
The syn_simd_access trap was never used so remove it. We should only see the COPROC encoding on v7 architectures. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 20260422125250.1303100-4-alex.bennee@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Alex Bennée committed
Apr 22, 2026 at 13:52 UTC
6581dddd2ee2f380db897f97dc19b253ba25b0dd
1 file changed
+15
-10
target/arm/syndrome.h
+15
-10
@@ -337,21 +337,26 @@ static inline uint32_t syn_cp15_rrt_trap(int cv, int cond, int opc1, int crm,
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return res;
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}
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+/*
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+ * ISS encoding for an exception from an access to a register of
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+ * instruction resulting from the FPEN or TFP traps.
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+ */
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+FIELD(FP_ISS, COPROC, 0, 4) /* ARMv7 only */
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+FIELD(FP_ISS, COND, 20, 4)
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+FIELD(FP_ISS, CV, 24, 1)
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+
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static inline uint32_t syn_fp_access_trap(int cv, int cond, bool is_16bit,
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int coproc)
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{
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/* AArch32 FP trap or any AArch64 FP/SIMD trap: TA == 0 */
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- return (EC_ADVSIMDFPACCESSTRAP << ARM_EL_EC_SHIFT)
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- | (is_16bit ? 0 : ARM_EL_IL)
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- | (cv << 24) | (cond << 20) | coproc;
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-}
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+ uint32_t res = syn_set_ec(0, EC_ADVSIMDFPACCESSTRAP);
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+ res = FIELD_DP32(res, SYNDROME, IL, !is_16bit);
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-static inline uint32_t syn_simd_access_trap(int cv, int cond, bool is_16bit)
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-{
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- /* AArch32 SIMD trap: TA == 1 coproc == 0 */
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- return (EC_ADVSIMDFPACCESSTRAP << ARM_EL_EC_SHIFT)
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- | (is_16bit ? 0 : ARM_EL_IL)
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- | (cv << 24) | (cond << 20) | (1 << 5);
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+ res = FIELD_DP32(res, FP_ISS, CV, cv);
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+ res = FIELD_DP32(res, FP_ISS, COND, cond);
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+ res = FIELD_DP32(res, FP_ISS, COPROC, coproc);
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+
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+ return res;
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}
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static inline uint32_t syn_sve_access_trap(void)