hw/usb/hcd-ehci.c: Fix coding style issues reported by checkpatch
No functional change. Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20260424080508.53992-5-jamin_lin@aspeedtech.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Jamin Lin committed
Mar 11, 2026 at 08:26 UTC
674a77a2f51be9f15327a979ab8ccddf281b0ff6
1 file changed
+71
-58
hw/usb/hcd-ehci.c
+71
-58
@@ -41,21 +41,23 @@
41
#define FRAME_TIMER_NS (NANOSECONDS_PER_SECOND / FRAME_TIMER_FREQ)
42
#define UFRAME_TIMER_NS (FRAME_TIMER_NS / 8)
43
44
-#define NB_MAXINTRATE 8 // Max rate at which controller issues ints
45
-#define BUFF_SIZE 5*4096 // Max bytes to transfer per transaction
46
-#define MAX_QH 100 // Max allowable queue heads in a chain
44
+#define NB_MAXINTRATE 8 /* Max rate at which controller issues ints */
45
+#define BUFF_SIZE (5 * 4096) /* Max bytes to transfer per transaction */
46
+#define MAX_QH 100 /* Max allowable queue heads in a chain */
47
#define MIN_UFR_PER_TICK 24 /* Min frames to process when catching up */
48
#define PERIODIC_ACTIVE 512 /* Micro-frames */
49
50
-/* Internal periodic / asynchronous schedule state machine states
50
+/*
51
+ * Internal periodic / asynchronous schedule state machine states
52
*/
53
typedef enum {
54
EST_INACTIVE = 1000,
55
EST_ACTIVE,
56
EST_EXECUTING,
57
EST_SLEEPING,
57
- /* The following states are internal to the state machine function
58
- */
58
+ /*
59
+ * The following states are internal to the state machine function
60
+ */
61
EST_WAITLISTHEAD,
62
EST_FETCHENTRY,
63
EST_FETCHQH,
@@ -71,13 +73,13 @@ typedef enum {
73
/* macros for accessing fields within next link pointer entry */
74
#define NLPTR_GET(x) ((x) & 0xffffffe0)
75
#define NLPTR_TYPE_GET(x) (((x) >> 1) & 3)
74
-#define NLPTR_TBIT(x) ((x) & 1) // 1=invalid, 0=valid
76
+#define NLPTR_TBIT(x) ((x) & 1) /* 1=invalid, 0=valid */
77
78
/* link pointer types */
77
-#define NLPTR_TYPE_ITD 0 // isoc xfer descriptor
78
-#define NLPTR_TYPE_QH 1 // queue head
79
-#define NLPTR_TYPE_STITD 2 // split xaction, isoc xfer descriptor
80
-#define NLPTR_TYPE_FSTN 3 // frame span traversal node
79
+#define NLPTR_TYPE_ITD 0 /* isoc xfer descriptor */
80
+#define NLPTR_TYPE_QH 1 /* queue head */
81
+#define NLPTR_TYPE_STITD 2 /* split xaction, isoc xfer descriptor */
82
+#define NLPTR_TYPE_FSTN 3 /* frame span traversal node */
83
84
#define SET_LAST_RUN_CLOCK(s) \
85
(s)->last_run_ns = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
@@ -88,10 +90,10 @@ typedef enum {
90
91
#define set_field(data, newval, field) do { \
92
uint32_t val = *data; \
91
- val &= ~ field##_MASK; \
93
+ val &= ~field##_MASK; \
94
val |= ((newval) << field##_SH) & field##_MASK; \
95
*data = val; \
94
- } while(0)
96
+ } while (0)
97
98
static const char *ehci_state_names[] = {
99
[EST_INACTIVE] = "INACTIVE",
@@ -472,8 +474,10 @@ static bool ehci_verify_pid(EHCIQueue *q, EHCIqtd *qtd)
474
}
475
}
476
475
-/* Finish executing and writeback a packet outside of the regular
476
- fetchqh -> fetchqtd -> execute -> writeback cycle */
477
+/*
478
+ * Finish executing and writeback a packet outside of the regular
479
+ * fetchqh -> fetchqtd -> execute -> writeback cycle
480
+ */
481
static void ehci_writeback_async_complete_packet(EHCIPacket *p)
482
{
483
EHCIQueue *q = p->queue;
@@ -733,7 +737,7 @@ static void ehci_detach(USBPort *port)
737
ehci_queues_rip_device(s, port->dev, 0);
738
ehci_queues_rip_device(s, port->dev, 1);
739
736
- *portsc &= ~(PORTSC_CONNECT|PORTSC_PED|PORTSC_SUSPEND);
740
+ *portsc &= ~(PORTSC_CONNECT | PORTSC_PED | PORTSC_SUSPEND);
741
*portsc |= PORTSC_CSC;
742
743
ehci_raise_irq(s, USBSTS_PCD);
@@ -858,7 +862,7 @@ void ehci_reset(void *opaque)
862
* Do the detach before touching portsc, so that it correctly gets send to
863
* us or to our companion based on PORTSC_POWNER before the reset.
864
*/
861
- for(i = 0; i < EHCI_PORTS; i++) {
865
+ for (i = 0; i < EHCI_PORTS; i++) {
866
devs[i] = s->ports[i].dev;
867
if (devs[i] && devs[i]->attached) {
868
usb_detach(&s->ports[i]);
@@ -877,7 +881,7 @@ void ehci_reset(void *opaque)
881
s->astate = EST_INACTIVE;
882
s->pstate = EST_INACTIVE;
883
880
- for(i = 0; i < EHCI_PORTS; i++) {
884
+ for (i = 0; i < EHCI_PORTS; i++) {
885
if (s->companion_ports[i]) {
886
s->portsc[i] = PORTSC_POWNER | PORTSC_PPOWER;
887
} else {
@@ -942,8 +946,9 @@ static void handle_port_owner_write(EHCIState *s, int port, uint32_t owner)
946
uint32_t *portsc = &s->portsc[port];
947
uint32_t orig;
948
945
- if (s->companion_ports[port] == NULL)
949
+ if (s->companion_ports[port] == NULL) {
950
return;
951
+ }
952
953
owner = owner & PORTSC_POWNER;
954
orig = *portsc & PORTSC_POWNER;
@@ -988,7 +993,7 @@ static void ehci_port_write(void *ptr, hwaddr addr,
993
trace_usb_ehci_port_reset(port, 1);
994
}
995
991
- if (!(val & PORTSC_PRESET) &&(*portsc & PORTSC_PRESET)) {
996
+ if (!(val & PORTSC_PRESET) && (*portsc & PORTSC_PRESET)) {
997
trace_usb_ehci_port_reset(port, 0);
998
if (dev && dev->attached) {
999
usb_port_reset(&s->ports[port]);
@@ -1065,8 +1070,10 @@ static void ehci_opreg_write(void *ptr, hwaddr addr,
1070
break;
1071
1072
case USBSTS:
1068
- val &= USBSTS_RO_MASK; // bits 6 through 31 are RO
1069
- ehci_clear_usbsts(s, val); // bits 0 through 5 are R/WC
1073
+ /* bits 6 through 31 are RO */
1074
+ val &= USBSTS_RO_MASK;
1075
+ /* bits 0 through 5 are R/WC */
1076
+ ehci_clear_usbsts(s, val);
1077
val = s->usbsts;
1078
ehci_update_irq(s);
1079
break;
@@ -1131,8 +1138,7 @@ static void ehci_flush_qh(EHCIQueue *q)
1138
put_dwords(q->ehci, addr + 3 * sizeof(uint32_t), qh + 3, dwords - 3);
1139
}
1140
1134
-// 4.10.2
1135
-
1141
+/* 4.10.2 */
1142
static int ehci_qh_do_overlay(EHCIQueue *q)
1143
{
1144
EHCIPacket *p = QTAILQ_FIRST(&q->packets);
@@ -1145,8 +1151,7 @@ static int ehci_qh_do_overlay(EHCIQueue *q)
1151
assert(p != NULL);
1152
assert(p->qtdaddr == q->qtdaddr);
1153
1148
- // remember values in fields to preserve in qh after overlay
1149
-
1154
+ /* remember values in fields to preserve in qh after overlay */
1155
dtoggle = q->qh.token & QTD_TOKEN_DTOGGLE;
1156
ping = q->qh.token & QTD_TOKEN_PING;
1157
@@ -1170,7 +1175,7 @@ static int ehci_qh_do_overlay(EHCIQueue *q)
1175
}
1176
1177
if (!(q->qh.epchar & QH_EPCHAR_DTC)) {
1173
- // preserve QH DT bit
1178
+ /* preserve QH DT bit */
1179
q->qh.token &= ~QTD_TOKEN_DTOGGLE;
1180
q->qh.token |= dtoggle;
1181
}
@@ -1397,9 +1402,7 @@ static int ehci_execute(EHCIPacket *p, const char *action)
1402
return 1;
1403
}
1404
1400
-/* 4.7.2
1401
- */
1402
-
1405
+/* 4.7.2 */
1406
static int ehci_process_itd(EHCIState *ehci,
1407
EHCIitd *itd,
1408
uint32_t addr)
@@ -1411,13 +1414,13 @@ static int ehci_process_itd(EHCIState *ehci,
1414
1415
ehci->periodic_sched_active = PERIODIC_ACTIVE;
1416
1414
- dir =(itd->bufptr[1] & ITD_BUFPTR_DIRECTION);
1417
+ dir = (itd->bufptr[1] & ITD_BUFPTR_DIRECTION);
1418
devaddr = get_field(itd->bufptr[0], ITD_BUFPTR_DEVADDR);
1419
endp = get_field(itd->bufptr[0], ITD_BUFPTR_EP);
1420
max = get_field(itd->bufptr[1], ITD_BUFPTR_MAXPKT);
1421
mult = get_field(itd->bufptr[2], ITD_BUFPTR_MULT);
1422
1420
- for(i = 0; i < 8; i++) {
1423
+ for (i = 0; i < 8; i++) {
1424
if (itd->transact[i] & ITD_XACT_ACTIVE) {
1425
pg = get_field(itd->transact[i], ITD_XACT_PGSEL);
1426
off = itd->transact[i] & ITD_XACT_OFFSET_MASK;
@@ -1513,8 +1516,9 @@ static int ehci_process_itd(EHCIState *ehci,
1516
}
1517
1518
1516
-/* This state is the entry point for asynchronous schedule
1517
- * processing. Entry here constitutes a EHCI start event state (4.8.5)
1519
+/*
1520
+ * This state is the entry point for asynchronous schedule
1521
+ * processing. Entry here constitutes a EHCI start event state (4.8.5)
1522
*/
1523
static int ehci_state_waitlisthead(EHCIState *ehci, int async)
1524
{
@@ -1531,7 +1535,7 @@ static int ehci_state_waitlisthead(EHCIState *ehci, int async)
1535
ehci_queues_rip_unused(ehci, async);
1536
1537
/* Find the head of the list (4.9.1.1) */
1534
- for(i = 0; i < MAX_QH; i++) {
1538
+ for (i = 0; i < MAX_QH; i++) {
1539
if (get_dwords(ehci, NLPTR_GET(entry), (uint32_t *) &qh,
1540
sizeof(EHCIqh) >> 2) < 0) {
1541
return 0;
@@ -1564,8 +1568,9 @@ out:
1568
}
1569
1570
1567
-/* This state is the entry point for periodic schedule processing as
1568
- * well as being a continuation state for async processing.
1571
+/*
1572
+ * This state is the entry point for periodic schedule processing as
1573
+ * well as being a continuation state for async processing.
1574
*/
1575
static int ehci_state_fetchentry(EHCIState *ehci, int async)
1576
{
@@ -1674,7 +1679,7 @@ static EHCIQueue *ehci_state_fetchqh(EHCIState *ehci, int async)
1679
1680
#if EHCI_DEBUG
1681
if (q->qhaddr != q->qh.next) {
1677
- DPRINTF("FETCHQH: QH 0x%08x (h %x halt %x active %x) next 0x%08x\n",
1682
+ DPRINTF("FETCHQH: QH 0x%08x (h %x halt %x active %x) next 0x%08x\n",
1683
q->qhaddr,
1684
q->qh.epchar & QH_EPCHAR_H,
1685
q->qh.token & QTD_TOKEN_HALT,
@@ -1756,7 +1761,8 @@ static int ehci_state_fetchsitd(EHCIState *ehci, int async)
1761
/* Section 4.10.2 - paragraph 3 */
1762
static int ehci_state_advqueue(EHCIQueue *q)
1763
{
1759
- /* TO-DO: 4.10.2 - paragraph 2
1764
+ /*
1765
+ * TO-DO: 4.10.2 - paragraph 2
1766
* if I-bit is set to 1 and QH is not active
1767
* go to horizontal QH
1768
*/
@@ -1929,8 +1935,10 @@ static int ehci_state_execute(EHCIQueue *q)
1935
return -1;
1936
}
1937
1932
- // TODO verify enough time remains in the uframe as in 4.4.1.1
1933
- // TODO write back ptr to async list when done or out of time
1938
+ /*
1939
+ * TODO verify enough time remains in the uframe as in 4.4.1.1
1940
+ * TODO write back ptr to async list when done or out of time
1941
+ */
1942
1943
/* 4.10.3, bottom of page 82, go horizontal on transaction counter == 0 */
1944
if (!q->async && q->transact_ctr == 0) {
@@ -2041,7 +2049,7 @@ static void ehci_advance_state(EHCIState *ehci, int async)
2049
int again;
2050
2051
do {
2044
- switch(ehci_get_state(ehci, async)) {
2052
+ switch (ehci_get_state(ehci, async)) {
2053
case EST_WAITLISTHEAD:
2054
again = ehci_state_waitlisthead(ehci, async);
2055
break;
@@ -2120,21 +2128,20 @@ static void ehci_advance_state(EHCIState *ehci, int async)
2128
ehci_reset(ehci);
2129
again = 0;
2130
}
2123
- }
2124
- while (again);
2131
+ } while (again);
2132
}
2133
2134
static void ehci_advance_async_state(EHCIState *ehci)
2135
{
2136
const int async = 1;
2137
2131
- switch(ehci_get_state(ehci, async)) {
2138
+ switch (ehci_get_state(ehci, async)) {
2139
case EST_INACTIVE:
2140
if (!ehci_async_enabled(ehci)) {
2141
break;
2142
}
2143
ehci_set_state(ehci, async, EST_ACTIVE);
2137
- // No break, fall through to ACTIVE
2144
+ /* No break, fall through to ACTIVE */
2145
2146
case EST_ACTIVE:
2147
if (!ehci_async_enabled(ehci)) {
@@ -2158,7 +2165,8 @@ static void ehci_advance_async_state(EHCIState *ehci)
2165
ehci_set_state(ehci, async, EST_WAITLISTHEAD);
2166
ehci_advance_state(ehci, async);
2167
2161
- /* If the doorbell is set, the guest wants to make a change to the
2168
+ /*
2169
+ * If the doorbell is set, the guest wants to make a change to the
2170
* schedule. The host controller needs to release cached data.
2171
* (section 4.8.2)
2172
*/
@@ -2185,13 +2193,13 @@ static void ehci_advance_periodic_state(EHCIState *ehci)
2193
uint32_t list;
2194
const int async = 0;
2195
2188
- // 4.6
2196
+ /* 4.6 */
2197
2190
- switch(ehci_get_state(ehci, async)) {
2198
+ switch (ehci_get_state(ehci, async)) {
2199
case EST_INACTIVE:
2200
if (!(ehci->frindex & 7) && ehci_periodic_enabled(ehci)) {
2201
ehci_set_state(ehci, async, EST_ACTIVE);
2194
- // No break, fall through to ACTIVE
2202
+ /* No break, fall through to ACTIVE */
2203
} else
2204
break;
2205
@@ -2215,7 +2223,7 @@ static void ehci_advance_periodic_state(EHCIState *ehci)
2223
2224
DPRINTF("PERIODIC state adv fr=%d. [%08X] -> %08X\n",
2225
ehci->frindex / 8, list, entry);
2218
- ehci_set_fetch_addr(ehci, async,entry);
2226
+ ehci_set_fetch_addr(ehci, async, entry);
2227
ehci_set_state(ehci, async, EST_FETCHENTRY);
2228
ehci_advance_state(ehci, async);
2229
ehci_queues_rip_unused(ehci, async);
@@ -2240,7 +2248,8 @@ static void ehci_update_frindex(EHCIState *ehci, int uframes)
2248
ehci_raise_irq(ehci, USBSTS_FLR);
2249
}
2250
2243
- /* How many times will frindex roll over 0x4000 with this frame count?
2251
+ /*
2252
+ * How many times will frindex roll over 0x4000 with this frame count?
2253
* usbsts_frindex is decremented by 0x4000 on rollover until it reaches 0
2254
*/
2255
int rollovers = (ehci->frindex + uframes) / 0x4000;
@@ -2320,8 +2329,9 @@ static void ehci_work_bh(void *opaque)
2329
ehci->async_stepdown++;
2330
}
2331
2323
- /* Async is not inside loop since it executes everything it can once
2324
- * called
2332
+ /*
2333
+ * Async is not inside loop since it executes everything it can once
2334
+ * called
2335
*/
2336
if (ehci_async_enabled(ehci) || ehci->astate != EST_INACTIVE) {
2337
need_timer++;
@@ -2339,15 +2349,18 @@ static void ehci_work_bh(void *opaque)
2349
}
2350
2351
if (need_timer) {
2342
- /* If we've raised int, we speed up the timer, so that we quickly
2343
- * notice any new packets queued up in response */
2352
+ /*
2353
+ * If we've raised int, we speed up the timer, so that we quickly
2354
+ * notice any new packets queued up in response
2355
+ */
2356
if (ehci->int_req_by_async && (ehci->usbsts & USBSTS_INT)) {
2357
expire_time = t_now +
2358
NANOSECONDS_PER_SECOND / (FRAME_TIMER_FREQ * 4);
2359
ehci->int_req_by_async = false;
2360
} else {
2349
- expire_time = t_now + (NANOSECONDS_PER_SECOND
2350
- * (ehci->async_stepdown+1) / FRAME_TIMER_FREQ);
2361
+ expire_time = t_now
2362
+ + (NANOSECONDS_PER_SECOND * (ehci->async_stepdown + 1) /
2363
+ FRAME_TIMER_FREQ);
2364
}
2365
timer_mod(ehci->frame_timer, expire_time);
2366
}