@samitouri / QOSamiQemu / commits / 6829acbfee

target/arm: GICv5 cpuif: Implement the GIC CDPRI instruction

Implement the CPU interface GIC CDPRI instruction, which is a wrapper around the SetPriority operation. As with the barrier insns, we omit for the moment details which are needed when the GICv5 supports virtualization: * traps when legacy GICv3 emulation is enabled * fine-grained-trap handling (which is done via registers that are new in GICv5) * sending the command for the virtual interrupt domain when inside a guest The CD instructions operate on the Current Physical Interrupt Domain, which is the one associated with the current security state and exception level. The spec also has the concept of a Logical Interrupt Domain, which is the one associated with the security state defined by SCR_EL3.{NS,NSE}. Mostly the logical interrupt domain is used by the LD instructions, which are EL3-only; but we will also want the concept later for handling some banked registers, so we define functions for both. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com> Message-id: 20260327111700.795099-20-peter.maydell@linaro.org

Peter Maydell committed Mar 27, 2026 at 11:16 UTC 6829acbfeef0fb85806e2e51ff85e20e631c59e3
1 file changed +58
target/arm/tcg/gicv5-cpuif.c
+58
@@ -10,6 +10,59 @@
10 #include "cpu.h"
11 #include "internals.h"
12 #include "cpregs.h"
13 +#include "hw/intc/arm_gicv5_stream.h"
14 +
15 +FIELD(GIC_CDPRI, ID, 0, 24)
16 +FIELD(GIC_CDPRI, TYPE, 29, 3)
17 +FIELD(GIC_CDPRI, PRIORITY, 35, 5)
18 +
19 +static GICv5Common *gicv5_get_gic(CPUARMState *env)
20 +{
21 + return env->gicv5state;
22 +}
23 +
24 +static GICv5Domain gicv5_logical_domain(CPUARMState *env)
25 +{
26 + /*
27 + * Return the Logical Interrupt Domain, which is the one associated
28 + * with the security state selected by the SCR_EL3.{NS,NSE} bits
29 + */
30 + switch (arm_security_space_below_el3(env)) {
31 + case ARMSS_Secure:
32 + return GICV5_ID_S;
33 + case ARMSS_NonSecure:
34 + return GICV5_ID_NS;
35 + case ARMSS_Realm:
36 + return GICV5_ID_REALM;
37 + default:
38 + g_assert_not_reached();
39 + }
40 +}
41 +
42 +static GICv5Domain gicv5_current_phys_domain(CPUARMState *env)
43 +{
44 + /*
45 + * Return the Current Physical Interrupt Domain as
46 + * defined by R_ZFCXM.
47 + */
48 + if (arm_current_el(env) == 3) {
49 + return GICV5_ID_EL3;
50 + }
51 + return gicv5_logical_domain(env);
52 +}
53 +
54 +static void gic_cdpri_write(CPUARMState *env, const ARMCPRegInfo *ri,
55 + uint64_t value)
56 +{
57 + GICv5Common *gic = gicv5_get_gic(env);
58 + uint8_t priority = FIELD_EX64(value, GIC_CDPRI, PRIORITY);
59 + GICv5IntType type = FIELD_EX64(value, GIC_CDPRI, TYPE);
60 + uint32_t id = FIELD_EX64(value, GIC_CDPRI, ID);
61 + bool virtual = false;
62 + GICv5Domain domain = gicv5_current_phys_domain(env);
63 +
64 + gicv5_set_priority(gic, id, priority, domain, type, virtual);
65 +}
66
67 static const ARMCPRegInfo gicv5_cpuif_reginfo[] = {
68 /*
@@ -33,6 +86,11 @@ static const ARMCPRegInfo gicv5_cpuif_reginfo[] = {
86 .opc0 = 1, .opc1 = 0, .crn = 12, .crm = 0, .opc2 = 1,
87 .access = PL1_W, .type = ARM_CP_NOP,
88 },
89 + { .name = "GIC_CDPRI", .state = ARM_CP_STATE_AA64,
90 + .opc0 = 1, .opc1 = 0, .crn = 12, .crm = 1, .opc2 = 2,
91 + .access = PL1_W, .type = ARM_CP_IO | ARM_CP_NO_RAW,
92 + .writefn = gic_cdpri_write,
93 + },
94 };
95
96 void define_gicv5_cpuif_regs(ARMCPU *cpu)